MAX4473
Detailed Description
The MAX4473 is a voltage-controlled, unidirectional,
high-side current setting amplifier for applications
where accurate control of PA supply current is desired.
This device is intended for wireless TDMA based sys-
tems (GSM, DECT), where tight restrictions over the
PA’s transmit burst and output power require closed-
loop control over the PA’s output power. When used
with a PA, the MAX4473 functions as a voltage-con-
trolled constant current source, accurately setting PA
supply current by varying the gain of the PA. If you
know the output power versus supply current profile for
the PA, you can set the PA’s output power by control-
ling the amount of supply current delivered to the PA.
The MAX4473 is composed of an input buffer (A1), a
voltage-to-current converting amplifier (A2), and a rail-
to-rail output error amplifier (A3) (see
Typical Operating
Circuit
). External gain and sense resistors allow pro-
grammability for a wide range of applications.
In the
Typical Operating Circuit
, PA supply current
flows from the system supply, through the external cur-
rent-sense resistor (R
SENSE
), to the PA. The rail-to-rail
outputs of the error amplifier, A3, adjust the gain of the
PA until the voltage drop across R
SENSE
equals the
voltage drop across external gain resistor, RG1. The
voltage drop across RG1 sets the voltage drop across
R
SENSE
, with a larger voltage drop resulting in more
current delivered to the PA. The voltage drop across
RG1 is set by A1, A2, and the V-to-I FET, Q1. A voltage
applied to the PC input of the input buffer is divided by
four by a resistor-divider network. A2 forces its inverting
input and the source of Q1 to V
PC
/ 4, thus setting a
voltage across RG3. The resulting current through RG3
sets the current through RG1. This unique architecture
allows the supply current to be set independent of sup-
ply voltage. Set PA supply current according to the fol-
lowing equation:
I
CCPA
= ( V
PC
· RG1 ) / ( 4 · R
SENSE
· RG3 )
Shutdown Mode
When SHDN is a logic-level low (SHDN < 0.4V), ampli-
fiers A1, A2, and A3 are off, Q1 is turned off, and the
output of A3 is actively pulled to ground with an N-
channel FET. Supply current is reduced to less than
1µA in shutdown mode. Typical power-up time is 0.9µs
and typical power-down time is 0.3µs, using the
MAX4473 test circuit.
Pin Description
Inverting Input of Error Amplifier and Drain of V-to-I FET, Q1. Connect to supply side of current-sense
, through gain resistor RG1.
Noninverting Input of Error Amplifier. Connect to load side of current-sense resistor, R
gain resistor RG2. Set RG2 equal to RG1.
Shutdown Input. Drive SHDN low to disable all amplifiers, pull OUT to GND, set the gate-to-source
voltage of the V-to-I FET (Q1) to 0, and reduce supply current to less than 1µA. Drive high or connect
for normal operation.
Power Control Input. Apply a voltage to PC to set a DC current through the sense resistor to control
PA bias.
Inverting Input to V-to-I Converter and Source of V-to-I FET, Q1. Connect to ground through gain
resistor RG3.
