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LTC1266CS-5#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
7
LTC1266
LTC1266-3.3/LTC1266-5
Pin 10 Connection Shown for LTC1266-3.3 and LTC1266-5; Changes Create LTC1266
+
–
16 4
1
3
15
PGND
BDRIVE
TDRIVE
PINV
BINH
2
PWR V
IN
R
S
Q
–
+
C
V
TRIP
7
13k
I
TH
PINV
1.265V
11 5
REFERENCE
–
+
SHDN V
IN
V
OS
–
+
V
G
9
SENSE
+
10
ADJUSTABLE
VERSION
V
FB
100k
5pF
–
+
V
TH1
T
–
+
V
TH2
S
SLEEP
12
SIGNAL
GROUND
6
C
T
OFF-TIME
CONTROL
MAX
ON-TIME
CONTROL
V
IN
SENSE
–
V
FB
SENSE
–
8
1266 FD
ENABLE
LB
OUT
LB
IN
V
IN
14
–
+
LB
13
1.25V
REFERENCE
The LTC1266 series uses a current mode, constant off-
time architecture to synchronously switch an external pair
of power MOSFETs. Operating frequency is set by an
external capacitor at the timing capacitor Pin 6.
The output voltage is sensed by an internal voltage divider
connected to SENSE
–
, Pin 8, (LTC1266-3.3 and LTC1266-
5) or external divider returned to V
FB
, Pin 10, (LTC1266).
A voltage comparator V, and a gain block G, compare the
divided output voltage with a reference voltage of 1.265V.
To optimize efficiency, the LTC1266 automatically switches
between two modes of operation, burst and continuous.
The voltage comparator is the primary control element
when the device is in Burst Mode
operation, while the gain
block controls the output voltage in continuous mode.
During the switch ON cycle in continuous mode, current
comparator C monitors the voltage between Pins 8 and 9
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the topside driver output is switched to
turn off the topside MOFSET (Power V
IN
for P-channel or
ground for N-channel). The timing capacitor connected to
Pin 6 is now allowed to discharge at a rate determined by
the off-time controller. The discharge current is made
proportional to the output voltage (measured by Pin 8) to
model the inductor current, which decays at a rate which
is also proportional to the output voltage. While the timing
capacitor is discharging, the bottom-side drive output is
switched to power V
IN
to turn on the bottom-side
N-channel MOSFET.
FU CTIO AL DIAGRA
U
U
W
OPERATIO
U
8
LTC1266
LTC1266 -3.3/LTC1266 -5
When the voltage on the timing capacitor has discharged
past V
TH1
, comparator T trips, setting the flip-
flop. This
causes the bottom-side output to switch off and the
topside output to switch on (ground for P-channel and
Power V
IN
for N-channel). The cycle then repeats.
As the load current increases, the output voltage decreases
slightly. This causes the output of the gain stage (Pin 7) to
increase the current comparator threshold, thus tracking
the load current.
The sequence of events for Burst Mode
operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the topside MOSFET
is held off by comparator V and the timing capacitor
continues to discharge below V
TH1
. When the timing
capacitor discharges past V
TH2
, voltage comparator S
trips, causing the internal sleep line to go low and the
bottom-side MOSFET to turn off.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, a majority of the
circuitry is turned off, dropping the quiescent current
from 2.1mA to 170µA. The load current is now being
supplied from the output capacitor. When the output
voltage has dropped by the amount of hysteresis in
comparator V, the topside MOSFET is again turned on
and this process repeats.
To avoid the operation of the current loop interfering with
Burst Mode
operation, a built-in offset V
OS
is incorporated
in the gain stage. This prevents the current comparator
threshold from increasing until the output voltage has
dropped below a minimum threshold.
One of the three basic LTC1266 application circuits is
shown in Figure 1. This circuit uses an N-channel
topside driver and a single supply. The other two circuit
configurations (see Typical Applications) use an
N-channel topside driver and dual supply, and a
P-channel topside driver. Selections of other external
components are driven by the load requirement and are
the same for all three circuit configurations. The first
step is the selection of R
SENSE
. Once R
SENSE
is known,
C
T
and L can be chosen. Next, the power MOSFETs and
D1 are selected. Finally, C
IN
and C
OUT
are selected and
the loop is compensated. Using an N-channel topside
switch, input voltages are limited to a maximum of
about 15V. With a P-channel, the input voltage may be
as high as 20V.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the
bottom-side drive output can turn on, the topside output
must be off. Likewise, the topside output is prevented
from turning on while the bottom-side drive output is
still on.
The LTC1266 has two select pins which provide the user
with choice of topside switch and with the option of
inhibiting Burst Mode operation. The phase select pin
allows the user to choose whether the topside MOSFET
is a P-channel or an N-channel. The phase select pin does
two things: sets the proper phase of the drive signal (ON
= Power V
IN
for N-channel and ON = 0V for P-channel)
and also sets an upper limit for the on-time (60µs) when
set to the N-channel. The on-time limit ensures proper
start-up when used in a single supply bootstrap circuit
configuration (see Applications Information). In P-channel
mode there is no on-time limit and thus, in dropout, the
P-channel MOSFET is turned on continuously (100%
duty cycle).
The Burst Mode operation inhibit (BINH, Pin 4) allows the
Burst Mode operation to be disabled by applying a CMOS
logic high to this pin. With Burst Mode operation disabled,
the LTC1266 will remain in continuous mode down to zero
load. Burst Mode operation is disabled by allowing the
lower current threshold limit to go below zero so that the
voltage comparator will never trip. The voltage comparator
trip point is also raised up so that it will not be tripped by
transients. It is still active to provide a voltage clamp to
prevent the output from overshooting.
OPERATIO
U
APPLICATIO S I FOR ATIO
WUUU
9
LTC1266
LTC1266-3.3/LTC1266-5
R
SENSE
Selection for Output Current
R
SENSE
is chosen based on the required output current.
The LTC1266 series current comparator has a threshold
range which extends from a minimum of 25mV/R
SENSE
(when Burst Mode operation is enabled) to a maximum of
155mV/R
SENSE
. The current comparator threshold sets
the peak of the inductor ripple current, yielding a maxi-
mum output current I
MAX
equal to the peak value less half
the peak-to-peak ripple current. For proper Burst Mode
operation, I
RIPPLE(P-P)
must be less than or equal to the
minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
I
RIPPLE(P-P)
= 25mV/R
SENSE
(see C
T
and L Selection for
Operating Frequency). Solving for R
SENSE
and allowing
a margin for variations in the LTC1266 series and
external component values yields:
R
SENSE
=
100mV
I
MAX
A graph for selecting R
SENSE
vs maximum output
current is given in Figure 2.
I
BURST
≈
15mV
R
SENSE
I
SC(PK)
=
155mV
R
SENSE
The LTC1266 series automatically extends t
OFF
during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
I
SC(AVG)
to be reduced to approximately I
MAX
.
L and C
T
Selection for Operating Frequency
The LTC1266 series uses a constant off-time architecture
with t
OFF
determined by an external timing capacitor C
T
.
Each time the topside MOSFET switch turns on, the
voltage on C
T
is reset to approximately 3.3V. During the
off-time, C
T
is discharged by a current which is propor-
tional to V
OUT
. The voltage on C
T
is analogous to the
current in inductor L, which likewise decays at a rate
proportional to V
OUT
. Thus the inductor value must track
the timing capacitor value.
The value of C
T
is calculated from the desired continuous
mode operating frequency, f:
C
T
=
1
2.6 • 10
4
•
f
assumes V
IN
= 2V
OUT
, (Figure 1 circuit).
A graph for selecting C
T
vs frequency including the effects
of input voltage is given in Figure 3.
Figure 2. Selecting R
SENSE
The load current, below which Burst Mode
operation
commences, (I
BURST
), and the peak short-circuit cur-
rent, (I
SC(PK)
), both track I
MAX
. Once R
SENSE
has been
chosen, I
BURST
and I
SC(PK)
can be predicted from the
following:
MAXIMUM OUTPUT CURRENT (A)
0
R
SENSE
(mΩ)
75
100
1266 F02
50
25
0
4
8
2
6
10
Figure 3. Timing Capacitor Value
FREQUENCY (kHz)
0
0
CAPACITANCE (pF)
200
400
100 200 300
400
1266 F03
600
800
500
V
IN
= 12V
V
IN
= 5V
V
OUT
= 3.3V
APPLICATIO S I FOR ATIO
WUUU
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC1266CS-5#TRPBF

Mfr. #:
Buy LTC1266CS-5#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Syn Switching Reg Controller
Lifecycle:
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