LTC1992 Family
30
1992fb
APPLICATIONS INFORMATION
The V
OCM
input pin has a very high input impedance and
is easily driven by even the weakest of sources. Many
ADCs provide a voltage reference output that defines
either its common mode level or its full-scale level. Apply
the ADC’s reference potential either directly to the V
OCM
pin or through a resistive voltage divider depending on
the reference voltage’s definition. When controlling the
V
OCM
pin by a high impedance source, connect a bypass
capacitor (1000pF to 0.1μF) from the V
OCM
pin to ground
to lower the high frequency impedance and limit external
noise coupling. Other applications will want the output
biased at a midpoint of the power supplies for maximum
output voltage swing. For these applications, the LTC1992
provides a mid-supply potential at the V
MID
pin. The V
MID
pin connects to a simple resistive voltage divider with
two 200k resistors connected between the supply pins.
To use this feature, connect the V
MID
pin to the V
OCM
pin
and bypass this node with a capacitor.
One undesired effect of utilizing the level shifting function
is an increase in the differential output offset voltage due to
gain setting resistor mismatch. The offset is approximately
the amount of level shift (V
OUTCM
– V
INCM
) multiplied by the
amount of resistor mismatch. For example, a 2V level shift
with 0.1% resistors will give around 2mV of output offset
(2 • 0.1% = 2mV). The exact amount of offset is dependent
on the application’s gain and the resistor mismatch. For a
detail description, consult the Fully Differential Amplifier
Applications Circuit Analysis section.
CMRR and Output Balance
One common misconception of fully differential amplifiers
is that the common mode level servo guarantees an infinite
common mode rejection ratio (CMRR). This is not true. The
common mode level servo does, however, force the two
outputs to be truly complementary (i.e., exactly opposite
or 180 degrees out of phase). Output balance is a measure
of how complementary the two outputs are.
At low frequencies, CMRR is primarily determined by the
matching of the gain setting resistors. Like any op amp, the
LTC1992 does not have infinite CMRR, however resistor
mismatching of only 0.018%, halves the circuit’s CMRR.
Standard 1% tolerance resistors yield a CMRR of about
40dB. For most applications, resistor matching dominates
low frequency CMRR performance. The specifications for
the fixed gain LTC1992-X parts include the on-chip resistor
matching effects. Also, note that an input common mode
signal appears as a differential output signal reduced by the
CMRR. As with op amps, at higher frequencies the CMRR
degrades. Refer to the Typical Performance plots for the
details of the CMRR performance over frequency.
At low frequencies, the output balance specification is
determined by the matching of the on-chip R
CMM
and
R
CMP
resistors. At higher frequencies, the output bal-
ance degrades. Refer to the typical performance plots
for the details of the output balance performance over
frequency.
Input Impedance
The input impedance for a fully differential amplifier ap-
plication circuit is similar to that of a standard op amp
inverting amplifier. One major difference is that the input
impedance is different for differential input signals and
single-ended signals. Referring to Figure 3, for differential
input signals the input impedance is expressed by the
following expression:
R
INDIFF
= 2 • R
IN
For single-ended signals, the input impedance is expressed
by the following expression:
R
INS-E
=
R
IN
1–
R
FB
2• R
IN
+ R
FB
()
The input impedance for single-ended signals is slightly
higher than the R
IN
value since some of the input signal
is fed back and appears as the amplifier’s input common
mode level. This small amount of positive feedback in-
creases the input impedance.
Driving Capacitive Loads
The LTC1992 family of parts is stable for all capacitive loads
up to at least 10,000pF. While stability is guaranteed, the
part’s performance is not unaffected by capacitive load-
ing. Large capacitive loads increase output step response
ringing and settling time, decrease the bandwidth and
increase the frequency response peaking. Refer to the
