MC74HCT273ADW

© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 12
1 Publication Order Number:
MC74HCT273A/D
MC74HCT273A
Octal D Flip-Flop with
Common Clock and Reset
with LSTTL-Compatible
Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT273A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT273A is identical in pinout to the LS273.
This device consists of eight D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active low.
Features
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 V to 5.5 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 284 FETs or 71 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
Figure 1. Logic Diagram
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
RESET
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
Q2
D1
D0
Q0
RESET
GND
Q3
D3
D2
Q1
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
CLOCK
Q4
D4
D5
Q5
http://onsemi.com
SOIC−20W
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
FUNCTION TABLE
Inputs Output
Reset Clock D Q
LXX L
HHH
HLL
H L X No Change
H X No Change
X = Don’t Care
Z = High Impedance
See detailed ordering and shipping information on page 4 o
f
this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
SOIC−20W TSSOP−20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
1
20
HCT
273A
ALYWG
G
20
1
HCT273A
AWLYYWWG
MC74HCT273A
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MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air SOIC Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 1) 0 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
−55 to
25_C
85_C 125_C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 μA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 μA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 μA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IH
or V
IL
|I
out
| 4.0 mA 4.5 3.98 3.84 3.7
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 μA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 4.0 mA 4.5 0.26 0.33 0.4
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 5.5 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 μA
5.5 4.0 40 160
mA
ΔI
CC
Additional Quiescent Supply
Current
V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0 mA
5.5
−55_C 25_C to 125_C
mA
2.9 2.4
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HCT273A
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3
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
Parameter Fig.
Guaranteed Limit
Unit
−55 to
25_C
85_C 125_C
f
max
Maximum Clock Frequency (50% Duty Cycle) 2, 5 30 24 20 MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q 2, 5 25 28 35 ns
t
PHL
Maximum Propagation Delay, Reset to Q 25 28 35 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output 2, 5 18 20 22 ns
C
PD
Power Dissipation Capacitance (Per Gate)*
Typical @ 25°C, V
CC
= 5.0 V
pF
30
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
TIMING REQUIREMENTS (V
CC
= 5.0 V ±10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter Fig.
Guaranteed Limit
Unit
–55 to 25_C 85_C 125_C
Min Max Min Max Min Max
t
su
Minimum Setup Time, Data to Clock 10 12 15 ns
t
h
Minimum Hold Time, Clock to Data 3.0 3.0 3.0 ns
t
rec
Minimum Recovery Time, Set or Reset Inactive to Clock 5.0 5.0 5.0 ns
t
w
Minimum Pulse Width, Clock 2 12 15 18 ns
t
w
Minimum Pulse Width, Set or Reset 12 15 18 ns
t
r
, t
f
Maximum Input Rise and Fall Times 2 500 500 500 ns
Figure 2.
C
LOCK
Q
t
r
t
f
3.0 V
GND
2.7 V
1.3 V
0.3 V
90%
1.3 V
10%
t
PLH
t
PHL
t
TLH
t
THL
Figure 3.
t
w
1/f
max
RESET
Q
CLOCK
t
w
1.3 V
1.3 V
1.3 V
3.0 V
GND
3.0 V
GND
t
PHL
t
rec
SWITCHING WAVEFORMS

MC74HCT273ADW

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC FF D-TYPE SNGL 8BIT 20SOIC
Lifecycle:
New from this manufacturer.
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