IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 14
IDT5V49EE901 REV S 071015
External I
2
C Interface Condition
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
Progread Command Frame
Progsave
Note:
PROGWRITE is for writing to the IDT5V49EE901 registers.
PROGREAD is for reading the IDT5V49EE901 registers.
PROGSAVE is for saving all the contents of the IDT5V49EE901 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the IDT5V49EE901 registers.
SAddress R/W
ACK Command Code ACK Register ACK Data ACK P
7-bits 0 1-bit 8-bits: xxxx xx00 1-bit 8-bits 1-bit 8-bits 1-bit
SAddress R/W ACK Command Code ACK Register ACK P
7-bits 0 1-bit 8-bits: xxxx xx00 1-bit 8-bits 1-bit
SAddressR/W ACK ID Byte ACK Data_1 ACK Data_2 ACK Data_last NACK P
7-bits 1 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit
SAddress R/W
ACK Command Code ACK P
7-bits 0 1-bit 8-bits: xxxx xx01 1-bit
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition