MC74VHC541DTG

© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 8
1 Publication Order Number:
MC74VHC541/D
MC74VHC541
Octal Bus Buffer
The MC74VHC541 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC541 is a noninverting type. When either OE1
or
OE2
are high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: t
PD
= 3.7ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 4 mA (Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP
= 1.2 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
OUTPUT
ENABLES
DATA
INPUTS
NONINVERTING
OUTPUTS
Figure 1. Logic Diagram
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See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1 OE2 A
L
H
Z
Z
PIN ASSIGNMENT
A5
A3
A2
A1
OE1
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Y3
Y2
Y1
OE2
V
CC
Y8
Y7
Y6
Y5
Y4
TSSOP−20
SUFFIX DT
CASE 948E
SOIC−20WB
SUFFIX DW
CASE 751D
1
1
20
20
See general marking information in the device marking
section on page 4 of this data sheet.
DEVICE MARKING INFORMATION
MC74VHC541
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage – 0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current − 20 mA
I
OK
Output Diode Current ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 +125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3V ±0.3V
V
CC
= 5.0V ±0.5V
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= − 55 to 125°C
Uni
t
Min Typ Max Min Max
V
IH
Minimum High−Level Input
Voltage
2.0
3.0 to 5.5
1.50
V
CC
x 0.7
1.50
V
CC
x 0.7
V
V
IL
Maximum Low−Level Input
Voltage
2.0
3.0 to 5.5
0.50
V
CC
x 0.3
0.50
V
CC
x 0.3
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
I
OH
= − 50mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= − 4mA
I
OH
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
I
OL
= 50mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
I
in
Maximum Input Leakage
Current
V
in
= 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0
mA
I
OZ
Maximum 3−State Leakage
Current
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ± 0.25 ± 2.5
mA
I
CC
Maximum Quiescent Supply
Current
V
in
= V
CC
or GND 5.5 4.0 40.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHC541
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3
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbo
l
Parameter Test Conditions
T
A
= 25°C T
A
= − 55 to 125°C
Uni
t
Min Typ Max Min Max
t
PLH
,
t
PHL
Maximum Propagation Delay,
A to Y
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
5.0
7.5
7.0
10.5
1.0
1.0
8.5
12.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
3.5
5.0
5.0
7.0
1.0
1.0
6.0
8.0
t
PZL
,
t
PZH
Output Enable TIme,
OE
to Y
V
CC
= 3.3 ± 0.3V C
L
= 15pF
R
L
= 1kW C
L
= 50pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
R
L
= 1kW C
L
= 50pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
t
PLZ
,
t
PHZ
Output Disable Time,
OE
to Y
V
CC
= 3.3 ± 0.3V C
L
= 50pF
R
L
= 1kW
11.2 15.4 1.0 17.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
R
L
= 1kW
6.0 8.8 1.0 10.0
t
OSLH
,
t
OSHL
Output to Output Skew
V
CC
= 3.3 ± 0.3V C
L
= 50pF
(Note 1)
1.5 1.5 ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
(Note 1)
1.0 1.0 ns
C
in
Maximum Input Capacitance 4 10 10 pF
C
out
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
6 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0V
pF
18
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
− t
PLHn
|, t
OSHL
= |t
PHLm
− t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/8 (per bit). C
PD
is used to determine the no−load
dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
Symbo
l
Parameter
T
A
= 25°C
Uni
t
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9 1.2 V
V
OLV
Quiet Output Minimum Dynamic V
OL
− 0.9 − 1.2 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
V
CC
GND
A
Y
t
PLH
OE1 or OE2
50%
V
CC
GND
Y
t
PZL
Y
t
PZH
HIGH
IMPEDANCE
V
OL
+0.3V
V
OH
-0.3V
HIGH
IMPEDANCE
t
PLZ
t
PHZ
50% V
CC
50% V
CC
t
PHL
50%
SWITCHING WAVEFORMS
50% V
CC
50%
Figure 2. Figure 3.

MC74VHC541DTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 2-5.5V Octal Bus
Lifecycle:
New from this manufacturer.
Delivery:
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