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NB3N3002DTG

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2013
May, 2017 − Rev. 7
1 Publication Order Number:
NB3N3002/D
NB3N3002
3.3V, Crystal to 25MHz,
100MHz, 125MHz and
200MHz HCSL Clock
Generator
Description
The NB3N3002 is a precision, low phase noise clock generator that
supports PCI−Express and Ethernet requirements. The device accepts
a 25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 5).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
• External Loop Filter is Not Required
• HCSL Differential Output or LVDS with Proper Termination
• For Selectable Multipliers of the Input Frequency
• Output Enable with Tri−State Outputs
• PCIe Gen1, Gen2, Gen3, Gen4, QPI, UPI Jitter Compliant
• Typical TIE RMS jitter of 2.5 ps
• Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz −109.4 dBc
1 kHz −127.8 dBc
10 kHz −136.2 dBc
100 kHz −138.8 dBc
1 MHz −138.2 dBc
10 MHz −161.4 dBc
20 MHz −163.00 dBc
• Operating Range 3.3 V ±5%
• Industrial Temperature Range −40°C to +85°C
• These are Pb−Free Devices
Figure 1. NB3N3002 Simplified Logic Diagram
Phase
Detector
Charge
Pump
HSCL
Output
BM
Clock Buffer
Crystal Oscillator
CLK
CLK
X1/CLK
X2
VCO
25 MHz Clock or
Crystal
GND
VDD
SEL0 SEL1 OE IREF
MARKING
DIAGRAM
TSSOP−16
DT SUFFIX
CASE 948F
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
1
16
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
NB3N
3002
ALYWG
G
1
16
(Note: Microdot may be in either location)
NB3N3002
www.onsemi.com
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0
SEL1
GND
X1/CLK
X2
OE
GND
GND
VDD
CLK
GND
VDD
NC
NC
IREF
CLK
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Symbol I/O Description
1 Sel0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to V
DD
. See output
select table 2 for details.
2 Sel1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to V
DD
. See output
select Table 2 for details.
12, 16 V
DD
Power Supply Positive supply voltage pins are connected to +3.3 V supply voltage.
4 X1/CLK Input Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock.
5 X2 Input Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.
6 OE Input Output enable tri−states output when connected to GND. Internal pullup resistor to V
DD
.
3, 7, 8, 13 GND Power Supply Ground 0 V. These pins provide GND return path for the devices.
9 I
REF
Output
Output current reference pin. Precision resistor (typ. 475 W) is connected from pin 9 to
GND to set the output current.
15 CLK HCSL or
LVDS Output
Noninverted clock output. (For LVDS levels see Figure 5)
14 CLK HCSL or
LVDS Output
Inverted clock output. (For LVDS levels see Figure 5)
10,11 NC Do not connect
Table 2. OUTPUT FREQUENCY SELECT TABLE
WITH 25MHz CRYSTALS
SEL1* SEL0* CLK Multiplier f
CLK
(MHz)
L L 1x 25
L H 4x 100
H L 5x 125
H H 8x 200
*Pins SEL1 and SEL0 default high when left open.
Recommended Crystal Parameters
Crystal Fundamental AT−Cut
Frequency 25 MHz
Load Capacitance 16−20 pF
Shunt Capacitance, C0 7 pF Max
Equivalent Series Resistance 50 W Max
Initial Accuracy at 25 °C ±20 ppm
Temperature Stability ±30 ppm
Aging ±20 ppm
NB3N3002
www.onsemi.com
3
Table 3. ATTRIBUTES
Characteristic Value
ESD Protection Human Body Model > 2 kV
RPU − OE, SEL0 and SEL1 Pull−up Resistor
100 kW
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 7623
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Symbol
Parameter Condition 1 Condition 2 Rating Units
V
DD
Positive Power Supply GND = 0 V 4.6 V
V
I
Input Voltage (V
IN
) GND = 0 V GND v V
I
v V
DD
−0.5 V to V
DD
+0.5 V V
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP–16
TSSOP–16
138
108
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) (Note 3) TSSOP−16 33 to 36 °C/W
T
sol
Wave Solder 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS (V
DD
= 3.3 V ±5%, GND = 0 V, T
A
= −40°C to +85°C)
Symbol Characteristic Min Typ Max Unit
I
DD
Power Supply Current (Note 4) 65 95 mA
I
DDOE
Power Supply Current when OE is Set Low 35 65 mA
V
IH
Input HIGH Voltage (X1/CLK, Sel0, Sel1,and OE) 0.7 * V
DD
V
DD
+ 300 mV
V
IL
Input LOW Voltage (X1/CLK, Sel0, Sel1, and OE) GND − 300 0.3* V
DD
mV
V
OH
Output HIGH Voltage (See Figure 4) 660 700 850 mV
V
OL
Output LOW Voltage (See Figure 4) −150 0 150 mV
V
cross
Crossing Voltage Magnitude (Absolute) 250 400 mV
DV
cross
Change in Magnitude of V
cross
150 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. NB3N circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Measurement taken with outputs terminated with R
S
= 33.2 W, R
L
= 49.9 W, with load capacitance of 2 pF and current biasing resistor, R
REF
,
from I
REF
(Pin 9) to GND of 475 W. See Figure 3.
P1-P3P4-P6P7-P8

NB3N3002DTG

Mfr. #:
Buy NB3N3002DTG
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL CLK GEN LVPECL DIFF OUT
Lifecycle:
New from this manufacturer.
Delivery:
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