RT9055
8
DS9055-02 August 2014www.richtek.com
©
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Applications Information
Like any low-dropout regulator, the external capacitors used
with the RT9055 must be carefully selected for regulator
stability and performance. Using a capacitor whose value
is >1μF on the RT9055 input and the amount of capacitance
can be increased without limit. The input capacitor must
be located a distance of not more than 0.5 inch from the
input pin of the IC and returned to a clean analog ground.
Any good quality ceramic or tantalum can be used for this
capacitor. The capacitor with larger value and lower ESR
(equivalent series resistance) provides better PSRR and
line-transient response.
The output capacitor must meet both requirements for
minimum amount of capacitance and ESR in all LDOs
application. The RT9055 is designed specifically to work
with low ESR ceramic output capacitor in space-saving
and performance consideration. Using a ceramic capacitor
whose value is at least 1μF with ESR is > 20mΩ on the
RT9055 output ensures stability. The RT9055 still works
well with output capacitor of other types due to the wide
stable ESR range. Figure 1 shows the curves of allowable
ESR range as a function of load current for various output
capacitor values. Output capacitor of larger capacitance
can reduce noise and improve load transient response,
stability, and PSRR. The output capacitor should be located
not more than 0.5 inch from the VOUT pin of the RT9055
and returned to a clean analog ground.
Figure 1. Stable C
OUT
ESR Range
Region of Stable C
OUT
ESR vs. Load Current
0.001
0.01
0.1
1
10
100
0 50 100 150 200 250 300
Load Current (mA)
Region of Stable C
OUT
ESR (Ω)
Region of Stable C
OUT
ESR (Ω)
Unstable Region
Stable Region
Simulation Verify
V
IN
= 5V, C
IN
= C
OUT1
=C
OUT2
=1μF/X7R
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. For WL-CSP-
6B 0.8x1.2 package, the thermal resistance, θ
JA
, is 148°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at T
A
= 25°C can be
calculated by the following formula :
P
D(MAX)
= (125°C − 25°C) / (148°C/W) = 0.670W
for WL-CSP-6B 0.8x1.2 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J (MAX)
and thermal
resistance, θ
JA
. The derating curves in Figure 2 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 2. Derating Curve of Maximum Power Dissipation
0.0
0.2
0.4
0.6
0.8
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
