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NCV7420D26R2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
NCV7420
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7
Figure 6. Operating Modes Transitions
EN
STB
TxD
Power off Standby
Normal
normal slope
Normal
low slope
Standby
Sleep
Wake−up (Local or LIN)
Standby
Power off
V
CC
V
BB
PORL_V
BB
V
BB_UV_th
NCV7420
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8
Electrical Characteristics
Definitions
All voltages are referenced to GND (Pin 11). Positive currents flow into the IC.
Table 6. ABSOLUTE MAXIMUM RATINGS – 3.3 V and 5 V versions
Symbol Parameter Min Max Unit
V
BB
Battery voltage on pin V
BB
(Note 11) −0.3 +45 V
V
CC
DC voltage on pin V
CC
0 +7 V
I
VCC
Current delivered by the V
CC
regulator 50 mA
V
LIN
LIN bus voltage (Note 12) −45 +45 V
V
INH
DC voltage on inhibit pin −0.3 V
BB
+ 0.3 V
V
WAKE
DC voltage on WAKE pin −45 45 V
V
DIG_IN
DC input voltage on pins TxD, RxD, EN, STB −0.3 V
CC
+ 0.3 V
T
J
Maximum junction temperature −40 +165 °C
V
ESD
Electrostatic discharge voltage on all pins; HBM (Note 13) −2 +2 kV
Electrostatic discharge voltage on LIN, INH, WAKE and V
BB
towards GND; HBM (Note 13) −4 +4 kV
Electrostatic discharge on LIN, WAKE and V
BB
; system HBM (Note 14) −8 +8 kV
Electrostatic discharge voltage on all pins; CDM (Note 16) −500 +500 V
V
ESD
(EMC/ESD
improved
versions)
Electrostatic discharge voltage on all pins; HBM (Note 13) −4 +4 kV
Electrostatic discharge voltage on LIN, INH, WAKE and V
BB
towards GND; HBM (Note 13) −6 +6 kV
Electrostatic discharge on LIN, WAKE and V
BB
; system HBM (Note 15) −12 +12 kV
Electrostatic discharge voltage on all pins; CDM (Note 16) −750 +750 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
11. The applied transients shall be in accordance with ISO 7637 part 1, test pulses 1, 2, 3a, 3b, and 5. The device complies with functional class
C; class A can be reached depending on the application and external components.
12.The applied transients shall be in accordance with ISO 7637 part 1, test pulses 1, 2, 3a, and 3b. The device complies with functional class
C; class A can be reached depending on the application and external components.
13.Equivalent to discharging a 100 pF capacitor through a 1500 W resistor.
14.Equivalent to discharging a 150 pF capacitor through a 330 W resistor conform to IEC Standard 61000−4−2. LIN bus filter 220 pF, V
BB
blocking
capacitor 100 nF, 3k3/10n R/C network on WAKE.
15.Equivalent to discharging a 150 pF capacitor through a 330 W resistor conform to IEC Standard 61000−4−2. No filter on LIN, V
BB
blocking
capacitor 100 nF, 3k3/10n R/C network on WAKE.
16.Charged device model according ESD-STM5.3.1.
NCV7420
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Table 7. DC CHARACTERISTICS – 3.3 V version
(V
BB
= 5 V to 26 V; T
J
= −40°C to +150°C; Bus Load = 500 W (V
BB
to LIN); unless otherwise specified.)
Symbol
Parameter Conditions Min Typ Max Unit
SUPPLY − Pin V
BB
I
BB_ON
Supply current Normal mode; LIN recessive 1.6 mA
I
BB_STB
Supply current Standby mode, V
BB
=
5–18 V, T
J
< 105°C
70
mA
I
BB_SLP
Supply current Sleep mode, V
BB
= 5–18 V,
T
J
< 105°C
20
mA
VOLTAGE REGULATOR − Pin V
CC
V
CC_OUT
Regulator output voltage
V
CC
load 1 mA − 30 mA 3.23 3.30 3.37
V
V
CC
load 0 mA − 50 mA 3.19 3.30 3.41
I
OUT_MAX_ABS
Absolute maximum output current Thermal shutdown must be
taken into account
50 mA
I
OUT_LIM
Overcurrent limitation 50 100 170 mA
DV
CC_OUT
Line Regulation (Note 22) V
BB
5−26 V, I
OUT
= 5 mA,
T
J
= 25°C
0.5 mV
Load Regulation (Note 22) I
OUT
1−50 mA, V
BB
= 14 V,
T
J
= 25°C
45 mV
V
DO
Dropout Voltage (V
BB
−V
CC_OUT
)
Figure 11, (Notes 21, 22)
I
OUT
= 1 mA, T
J
= 25°C 13 mV
I
OUT
= 10 mA, T
J
= 25°C 134 mV
I
OUT
= 50 mA, T
J
= 25°C 732 mV
LIN TRANSMITTER − Pin LIN
V
LIN_dom_LoSup
LIN dominant output voltage TxD = low; V
BB
= 7.3 V 1.2 V
V
LIN_dom_HiSup
LIN dominant output voltage TxD = low; V
BB
= 18 V 2.0 V
V
LIN_REC
LIN Recessive Output Voltage (Note 17)
TxD = high; I
LIN
= 10 mA
V
BB
− 1.5 V
BB
V
I
LIN_lim
Short circuit current limitation V
LIN
= V
BB_MAX
40 200 mA
R
SLAVE
Internal pull−up resistance 20 33 47
kW
C
LIN
Capacitance on pin LIN (Note 19) 15 25 pF
LIN RECEIVER − Pin LIN
V
bus_dom
Bus voltage for dominant state 0.4 V
BB
V
bus_rec
Bus voltage for recessive state 0.6 V
BB
V
rec_dom
Receiver threshold LIN bus recessive → dominant 0.4 0.6 V
BB
V
rec_rec
Receiver threshold LIN bus dominant → recessive 0.4 0.6 V
BB
V
rec_cnt
Receiver centre voltage (Vrec_dom + Vrec_rec) / 2 0.475 0.525 V
BB
V
rec_hys
Receiver hysteresis (Vrec_rec − Vrec_dom) 0.05 0.175 V
BB
I
LIN_off_dom
LIN output current bus in dominant state Driver off; V
BB
= 12 V,
V
LIN
= 0 V
−1 mA
I
LIN_off_rec
LIN output current bus in recessive state Driver off; V
BB
< 18 V
V
BB
< V
LIN
< 18 V
1
mA
I
LIN_no_GND
Communication not affected V
BB
= GND = 12 V;
0 < V
LIN
< 18 V
−1 1 mA
17.The voltage drop in Normal mode between LIN and V
BB
pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
at the switch is negligible. See Figure 1.
18.By one of the trimming bits, following reconfiguration can be done during chip−level testing in order to fit the NCV7420−3 into different
interface: pins TxD and EN will have typ. 10 kW pull−down resistor to ground and pin WAKE will have typ. 10 mA pull−up current source.
19.Guaranteed by design. Not tested.
20.V
BB
undervoltage threshold is always higher than V
BB
POR low level (V
BB_UV_th
> PORL_V
BB
)
21.Measured at output voltage V
CC_OUT
= (V
CC_OUT
@V
BB
= 5 V) – 2%.
22.Values based on design and characterization. Not tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

NCV7420D26R2G

Mfr. #:
Buy NCV7420D26R2G
Manufacturer:
ON Semiconductor
Description:
LIN Transceivers EMC IMPR. LIN + 5V REGULATOR
Lifecycle:
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