CY62256
Document #: 38-05248 Rev. *E Page 4 of 13
AC Test Loads and Waveforms
Data Retention Characteristics
Parameter Description Conditions
[6]
Min. Typ.
[2]
Max. Unit
V
DR
V
CC
for Data Retention 2.0 V
I
CCDR
Data Retention Current L V
CC
= 3.0V, CE > V
CC
0.3V,
V
IN
> V
CC
0.3V, or V
IN
< 0.3V
250µA
LL 0.1 5 µA
LL - Ind’l 0.1 10 µA
LL - Auto 0.1 10 µA
t
CDR
[5]
Chip Deselect to Data Retention Time 0 ns
t
R
[5]
Operation Recovery Time t
RC
ns
3.0V
5V
OUTPUT
R1 1800
R2
990
100 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns
<5ns
5V
OUTPUT
R1 1800
R2
990
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.77V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
639
Data Retention Waveform
Note:
6. No input may exceed V
CC
+ 0.5V.
3.0V3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
CY62256
Document #: 38-05248 Rev. *E Page 5 of 13
Switching Characteristics Over the Operating Range
[7]
Parameter Description
CY6225655 CY6225670
UnitMin. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 55 70 ns
t
AA
Address to Data Valid 55 70 ns
t
OHA
Data Hold from Address Change 5 5 ns
t
ACE
CE LOW to Data Valid 55 70 ns
t
DOE
OE LOW to Data Valid 25 35 ns
t
LZOE
OE LOW to Low-Z
[8]
55ns
t
HZOE
OE HIGH to High-Z
[8, 9]
20 25 ns
t
LZCE
CE LOW to Low-Z
[8]
55ns
t
HZCE
CE HIGH to High-Z
[8, 9]
20 25 ns
t
PU
CE LOW to Power-up 0 0 ns
t
PD
CE HIGH to Power-down 55 70 ns
Write Cycle
[10, 11]
t
WC
Write Cycle Time 55 70 ns
t
SCE
CE LOW to Write End 45 60 ns
t
AW
Address Set-up to Write End 45 60 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-up to Write Start 0 0 ns
t
PWE
WE Pulse Width 40 50 ns
t
SD
Data Set-up to Write End 25 30 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High-Z
[8, 9]
20 25 ns
t
LZWE
WE HIGH to Low-Z
[8]
55ns
Switching Waveforms
Read Cycle No. 1
[12, 13]
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10.The internal Write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
12.Device is continuously selected. OE
, CE = V
IL
.
13. WE
is HIGH for Read cycle.
ADDRESS
DATA OUT PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
CY62256
Document #: 38-05248 Rev. *E Page 6 of 13
Read Cycle No. 2
[13, 14]
Write Cycle No. 1 (WE Controlled)
[10, 15, 16]
Write Cycle No. 2 (CE Controlled)
[10, 15, 16]
Notes:
14.Address valid prior to or coincident with CE
transition LOW.
15.Data I/O is high impedance if OE
= V
IH
.
16. If CE
goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17.During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE
17
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
CE
DATA
IN
VALID

CY62256L-70SNXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 256K PARALLEL 28SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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