Dual Low Power PLL
Frequency Synthesizer
Data Sheet
ADF4212L
Rev. E Document Feedback
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FEATURES
I
DD
total: 7.5 mA
Bandwidth RF/IF: 2.4 GHz/1.0 GHz
2.7 V to 3.3 V power supply
Separate V
P
allows extended tuning voltage
Programmable dual modulus prescaler
RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Fastlock mode
Power-down mode
20-lead TSSOP and 20-lead LFCSP packages
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA,
WCDMA)
Base stations for wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Cable TV tuners (CATV)
Communications test equipment
GENERAL DESCRIPTION
The ADF4212L is a dual frequency synthesizer that can be used
to implement local oscillators (LO) in the up-conversion and
down-conversion sections of wireless receivers and transmitters.
It can provide the LO for both the RF and IF sections. It consists
of a low noise digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual modulus prescaler (P/P + 1). The
A (6-bit) and B (12-bit) counters, in conjunction with the dual
modulus prescaler (P/P + 1), implement an N divider (N = BP +
A). In addition, the 15-bit reference counter (R counter) allows
selectable REF
IN
frequencies at the PFD input. A complete phase-
locked loop (PLL) can be implemented if the synthesizer is used
with external loop filters and voltage controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface with 1.8 V compatibility. The devices operate with a
power supply ranging from 2.7 V to 3.3 V and can be powered
down when not in use.
FUNCTIONAL BLOCK DIAGRAM
RF
IN
IF
PRESCALER
DGND
RF
AGND
RF
DGND
IF
AGND
IF
R
SET
FL
O
SWITCH
FL
O
R
SET
V
DD
1 V
DD
2 V
P
1 V
P
2
REF
IN
IF
IN
CLK
ADF4212L
DATA
LE
22-BIT
DATA
REGISTER
SDOUT
15-BIT RF
R-COUNTER
15-BIT IF
R-COUNTER
12-BIT RF
B-COUNTER
12-BIT IF
B-COUNTER
IF PHASE
FREQUENCY
DETECTOR
02774-001
IF
LOCK
DETECT
IFCP3 IFCP2
IF CURRENT
SETTING
CHARGE
PUMP
REFERENCE
IFCP1
RFCP3 RFCP2
OUTPUT
MUX
REFERENCE
REFERENCE
RF PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
RFCP1
6-BIT RF
A-COUNTER
6-BIT IF
A-COUNTER
RF
PRESCALER
OSCILLATOR
RF
LOCK
DETECT
MUXOUT
CP
IF
CP
RF
Figure 1.
ADF4212L* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Application Notes
AN-30: Ask the Applications Engineer - PLL Synthesizers
AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
ADF4212L: Dual Low Power PLL Frequency Synthesizer
Data Sheet
TOOLS AND SIMULATIONS
ADIsimPLL™
ADIsimRF
REFERENCE MATERIALS
Product Selection Guide
RF Source Booklet
Technical Articles
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 1
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 3
Phase-Locked Loops for High-Frequency Receivers and
Transmitters - Part 2
DESIGN RESOURCES
ADF4212L Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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number.
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ADF4212L Data Sheet
Rev. E | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Circuit Description ......................................................................... 13
Reference Input Section ............................................................. 13
RF/IF Input Stage........................................................................ 13
Prescaler (P/P + 1) ...................................................................... 13
RF/IF A and B Counters ............................................................ 13
Pulse Swallow Function ............................................................. 13
RF/IF R Counter ......................................................................... 13
Phase Frequency Detector (PFD) and Charge Pump ............ 14
MUXOUT and Lock Detect ...................................................... 14
Lock Detect ................................................................................. 14
RF/IF Input Shift Register ......................................................... 14
IF R Counter Latch ..................................................................... 16
IF N Counter Latch .................................................................... 17
RF R Counter Latch ................................................................... 18
RF N Counter Latch ................................................................... 19
Program Modes .............................................................................. 20
IF and RF Power-Down ............................................................. 20
IF Section ..................................................................................... 20
RF Section ................................................................................... 21
Applications Information .............................................................. 22
Local Oscillator for GSM Handset Receiver ............................... 22
Wideband PLL ............................................................................ 23
Interfacing ................................................................................... 24
PCB Design Guidelines for Lead Frame
Chip Scale Package ..................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
1/14—Rev. D to Rev. E
Changes to Table 10 ........................................................................ 18
8/12—Rev. C to Rev D
Changed CP-20-1 to CP-20-6 ........................................... Universal
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
11/10—Rev. B to Rev C
Changes to V
P
1, V
P
2 to GND Parameter, Table 4 and V
P
1, V
P
2
to V
DD
1, V
DD
2 Parameter, Table 4 ................................................... 6
Changes to Ordering Guide .......................................................... 26
9/08—Rev. A to Rev B
Updated Format .................................................................. Universal
Changes to Figure 1 and General Description Section ............... 1
Changes to Prescaler Output Frequency Parameter and RF
Input Frequency (RF
IN
) Parameter ................................................. 3
Changes to Table 3 and Figure 2 ..................................................... 5
Changes to Figure 4 .......................................................................... 7
Changes to Figure 27, RF/IF A and B Counters Section, Pulse
Swallow Function Section, and RF/IF R Counter Section ........ 13
Changes to RF/IF Input Shift Register Section ........................... 14
Changes to Programmable IF Reference (R) Counter Section,
IF Program Modes Section, and IF Power-Down Section ........ 20
Changes to Programmable RF Reference (R) Counter Section,
RF Program Modes Section, Programmable RF N Counter
Section, and RF Power-Down Section ......................................... 21
Changes to Figure 32 ...................................................................... 23
Changes to Figure 33 and Figure 34............................................. 24
Added PCB Design Guidelines for Lead Frame Chip Scale
Package Section............................................................................... 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
3/03—Data Sheet changed from REV. 0 to REV. A
Changes to General Description ..................................................... 1
Changes to Specifications ................................................................. 3
Changes to Table 9 .......................................................................... 18
Changes to Table 11 ....................................................................... 20
Changes to Figure 31 ...................................................................... 23
11/02—Revision 0: Initial Version

ADF4212LBCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Dual Power Freq Synthesizer
Lifecycle:
New from this manufacturer.
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