FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FIN24C Rev. 1.0.2 17
Notes:
4. Typical Values are given for V
DD
= 2.775V and T
A
= 25°C. Positive current values refer to the current flowing into
device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise
specified (except ΔV
OD
and V
OD
).
5. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
6. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies based
on the operating mode of the device.
7. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the clock
remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total
measured input skew is a combination of output skew from the serializer, load variations, and ISI and jitter effects.
8. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP
occurs approximately eight bit times after a data transition or six bit times after the first falling edge of CSKO. Variation
of the data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path
and propagation delay differences on the various data pins. If the CKREF is not equal to STROBE for the serializer,
the CKP signal does not maintain a 50% duty cycle. The low time of the CKP remains 13 bit times.
Control Logic Timing Controls
Note:
9. Deserializer enable time includes the amount of time required for internal voltage and current references to stabilize.
This time is significantly less than the PLL lock time and does not impact overall system startup time.
Capacitance
Symbol Parameter Test Conditions Min. Typ. Max. Units
t
PHL_DIR
,
t
PLH_DIR
Propagation Delay
DIRI-to-DIRO
DIRI LOW-to-HIGH or HIGH-to-LOW 17.0 ns
t
PLZ
, t
PHZ
Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH 25.0 ns
t
PZL
, t
PZH
Propagation Delay
DIRI-to-DP
DIRI HIGH-to-LOW 25.0 ns
t
PLZ
, t
PHZ
Deserializer Disable Time:
S0 or S1 to DP
DIRI = 0,
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30
25.0 ns
t
PZL
, t
PZH
Deserializer Enable Time:
S0 or S1 to DP
DIRI = 0,
(10)
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30
2.0 µs
t
PLZ
, t
PHZ
Serializer Disable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 28
25.0 ns
t
PZL
, t
PZH
Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH, Figure 28
65.0 ns
Symbol Parameter Test Conditions Min. Typ. Max. Units
C
IN
Capacitance of Input Only Signals,
CKREF, STROBE, S1, S2, DIRI
DIRI = 1, S1 = S2 = 0,
V
DDP
= 2.5V
2.0 pF
C
IO
Capacitance of Parallel Port Pins
DP[1:12]
DIRI = 1, S1 = S2 = 0,
V
DDP
= 2.5V
2.0 pF
C
IO-DIFF
Capacitance of Differential I/O Signals DIRI = 0, S1 = S2 = 0,
V
DDP
= 2.775V
2.0 pF
