74AHC_AHCT594_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 4 July 2013 12 of 24
NXP Semiconductors 74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
[1] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
=5.0V).
[2] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
t
PHL
HIGH to LOW
propagation
delay
SHCP to Q7S; see Figure 9
C
L
= 15 pF - 4.1 6.7 1.8 7.6 1.8 8.3 ns
C
L
= 50 pF - 5.4 8.8 2.4 10.1 2.4 11.0 ns
STCP to Qn; see Figure 10
C
L
= 15 pF - 3.7 6.1 1.9 6.9 1.9 7.2 ns
C
L
= 50 pF - 5.2 8.5 2.6 9.7 2.6 10.5 ns
SHR
to Q7S; see Figure 13
C
L
= 15 pF - 4.3 7.0 2.4 8.0 2.4 8.7 ns
C
L
= 50 pF - 5.4 8.8 2.7 10.1 2.7 11.0 ns
STR
to Qn; see Figure 14
C
L
= 15 pF - 4.5 7.4 2.3 8.4 2.3 9.2 ns
C
L
= 50 pF - 5.7 9.4 3.1 10.7 3.1 11.7 ns
f
max
maximum
frequency
SHCP or STCP;
see Figure 9 and Figure 10
90 160 - 80 - 70 - MHz
t
W
pulse width SHCP and STCP HIGH or
LOW; see Figure 9 and
Figure 10
5.5 - - 6.0 - 6.5 - ns
SHR
and STR HIGH or LOW;
see Figure 13 and Figure 14
5.2 - - 5.5 - 6.0 - ns
t
su
set-up time DS to SHCP; see Figure 11 3.0 - - 3.0 - 3.5 - ns
SHR
to STCP; see Figure 12 5.0 - - 5.0 - 5.5 - ns
SHCP to STCP; see Figure 10
5.0 - - 5.0 - 5.5 - ns
t
h
hold time DS to SHCP; see Figure 11 2.0 - - 2.0 - 2.5 - ns
t
rec
recovery time SHR to SHCP; see Figure 13 2.9 - - 3.3 - 3.8 - ns
STR
to STCP; see Figure 14 3.4 - - 3.8 - 4.3 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
= GND to V
CC
[2]
-55- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
74AHC_AHCT594_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 4 July 2013 13 of 24
NXP Semiconductors 74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
12. Waveforms
Measurement points are given in Table 8.
Fig 9. Shift register clock pulse width, maximum frequency and input to output propagation delays
001aae341
SHCP input
Q7S output
V
M
t
PLH
t
TLH
t
THL
t
PHL
V
M
t
W
1/f
max
Measurement points are given in Table 8.
Fig 10. Shift register clock to storage register clock set-up time and storage clock pulse width, maximum
frequency and input to output propagation delays
V
M
t
W
1/f
max
V
M
V
M
t
su
t
PLH
Qn outputs
STCP input
SHCP input
t
PHL
mla512
74AHC_AHCT594_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 4 July 2013 14 of 24
NXP Semiconductors 74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 11. Shift register clock to data input set-up and hold times
001aae342
t
h
t
su
t
h
t
su
V
M
V
M
V
M
Q7 output
SH
CP input
D
S input
Measurement points are given in Table 8.
Fig 12. Storage register reset pulse width, input to output propagation delay and recovery time
mbc325
V
M
t
PHL
V
M
t
rec
t
W
V
M
STCP input
Q
n outputs
STR input

74AHCT594PW-Q100,1

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 74AHCT594PW-Q100/TSSOP16/REEL
Lifecycle:
New from this manufacturer.
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