91305AGILF

ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER 4
ICS91305I REV G 090612
Switching Characteristics
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Output period t1 With CL=30pF
100.00
(10)
7.5
(133)
ns
(MHz)
Input period t1 With CL=30pF
100.00
(10)
7.5
(133)
ns
(MHz)
Duty Cycle
1
Dt1 Measured at 1.4V; CL=30pF 40.0 50 60 %
Duty Cycle
1
Dt2
Measured at VDD/2 Fout
<66.6MHz
45 50 55 %
Rise Time
1
tr1
Measured between 0.8V and 2.0V:
CL=30pF
1.2 1.5 ns
Fall Time
1
tf1
Measured between 2.0V and 0.8V;
CL=30pF
1.2 1.5 ns
Delay, REF Rising
Edge to CLKOUT
Rising Edge
1, 2
Dr1 Measured at 1.4V 0 ±350 ps
Output to Output
Skew
1
Tskew
All outputs equally loaded,
CL=20pF
250 ps
Device to Device
Skew
1
Tdsk-Tdsk
Measured at VDD/2 on the
CLKOUT pins of devices
0 700 ps
Cycle to Cycle
Jitter
1
Tcyc-Tcyc
Measured at 66.66 MHz, loaded
outputs
200 ps
PLL Lock Time
1
t
LOCK
Stable power supply, valid clock
presented on REF pin
1.0 ms
Jitter; Absolute
Jitter
1
Tjabs
@ 10,000 cycles
C
L
= 30pF
-200 70 200 ps
Jitter; 1 - Sigma
1
Tj1s
@ 10,000 cycles
C
L
= 30pF
14 60 ps
ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER 5
ICS91305I REV G 090612
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of
the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase
difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than
CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to
have different rise times and different times crossing the measurement thresholds.
Timing diagrams with different loading configurations
ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER 6
ICS91305I REV G 090612
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
8
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004)
C
C
L
H
h x 45
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.33 0.51 .013 .020
C 0.19 0.25 .0075 .0098
D 4.80 5.00 .1890 .1968
E 3.80 4.00 .1497 .1574
e 1.27 BASIC 0.050 BASIC
H 5.80 6.20 .2284 .2440
h 0.25 0.50 .010 .020
L 0.40 1.27 .016 .050
α 0° 8° 0° 8°

91305AGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low SKEW BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet