22©2016 Integrated Device Technology, Inc. Revision F, January 14, 2016
853S111B Datasheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 32-Lead VFQFN
Table 9. Package Dimensions
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin-out are shown on the front page. The
package dimensions are in Table 9.
To p View
Index Area
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 08 C
C
A3
A1
S eating Plan e
E2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Base
N
OR
Anvil
Singulation
N-1N
CHAMFER
1
2
N-1
1
2
N
RADIUS
4
4
Bottom View w/Type C IDBottom View w/Type A ID
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 32
A 0.80 1.00
A1 00.05
A3 0.25 Ref.
b 0.18 0.25 0.30
N
D
& N
E
8
D & E 5.00 Basic
D2 & E2 3.0 3.3
e 0.50 Basic
L 0.30 0.40 0.50
23©2016 Integrated Device Technology, Inc. Revision F, January 14, 2016
853S111B Datasheet
Ordering Information
Table 10. Ordering Information
Table 11. Pin 1 Orientation in Tape and Reel Packaging
Part/Order Number Marking Package Shipping Packaging Temperature
853S111BYILF ICS53S111BIL 32-Lead TQFP, E-Pad Tray -40C to 85C
853S111BYILFT ICS53S111BIL 32-Lead TQFP, E-Pad Tape & Reel -40C to 85C
853S111BKILF ICS3S111BIL 32-Lead VFQFN Tray -40C to 85C
853S111BKILFT ICS3S111BIL 32-Lead VFQFN Tape & Reel, pin 1 orientation: EIA-481-C -40C to 85C
853S111BKILF/W ICS3S111BIL 32-Lead VFQFN Tape & Reel, pin 1 orientation EIA-481-D -40C to 85C
Part Number Suffix Pin 1 Orientation Illustration
T Quadrant 1 (EIA-481-C)
/W Quadrant 2 (EIA-481-D)
24©2016 Integrated Device Technology, Inc. Revision F, January 14, 2016
853S111B Datasheet
Revision History Sheet
Rev Table Page Description of Change Date
B
T6A
T7A
T10
1
17
19
22
Added 32-Lead VFQFN Pin Assignment and all references throughout the datasheet.
Thermal Resistance Table, updated theta ja numbers.
Thermal Resistance, updated theta ja numbers.
Ordering Information Table - added 32-Lead VFQFN ordering information.
11/18/2011
C T5 7 Added 0.13 value to Max columns for tjit Buffer Additive Phase Jitter, RMS. 4/5/2012
C
T10
1
11
22
Added CML to 3rd bullet.
Added figures 3E and 3F.
Deleted quantity from tape and reel.
10/29/2012
C
T10
10
13
21
22
Updated Wiring the Differential Inputs to Accept Single-ended Levels application note.
Corrected diagrams in application note, Termination for 2.5V LVPECL Outputs,
Corrected 32-Lead VFQFN Package Outline
Ordering Information Table - corrected 32-Lead TQFP packaging column from Tube to
Tray.
6/12/2013
C T4C 5 Added V
BB,
Output Reference row to table 4C. 1/10/2014
D
T4B
T4C
5
6
LVPECL DC Characteristics Table - added V
CMR1
and V
CMR2
specs.
Change Note 4, and added Note 5.
LVPECL DC Characteristics Table - added V
CMR1
and V
CMR2
specs.
Change Note 4, and added Note 5.
Deleted “ICS” prefix from part number throughout the datasheet.
6/15/15
E
T11
T10
23 Added P1 orientation for Tape and Reel table.
Ordering information Table - Added W part number.
6/30/15
F
11 Applications Information Section - added Wiring the Differential Input to Accept
single-ended LVPECL Levels.
Updated datasheet header/footer.
1/14/16

853S111BKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer FANOUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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