ADCMP562BRQ Datasheet ADCMP561BRQZ, ADCMP562BRQZ-RL7, ADCMP562BRQ | P10-P12

ADCMP561/ADCMP562 Data Sheet

Rev. B | Page 10 of 14

TIMING INFORMATION

Figure 18 shows the compare and latch features of the ADCMP561/ADCMP562. Table 4 describes the terms in the diagram.

50%

REF

± V

50%

DIFFERENTIAL

INPUT VOLTAGE

LATCH ENABLE

Q OUTPUT

LATCH ENABLE

PDL

PDH

PLOH

PLOL

04687-0-004

Figure 18. System Timing Diagram

Table 4. Timing Descriptions

Symbol Timing Description

PDH

Input to Output High Delay Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition.

PDL

Input to Output Low Delay Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output high-to-low transition.

PLOH

Latch Enable to Output High Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition.

PLOL

Latch Enable to Output Low Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output high-to-low transition.

Minimum Hold Time Minimum time after the negative transition of the latch enable signal that the input signal

must remain unchanged to be acquired and held at the outputs.

Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change.

Minimum Setup Time Minimum time before the negative transition of the latch enable signal that an input

signal change must be present to be acquired and held at the outputs.

Output Rise Time

Amount of time required to transition from a low to a high output as measured at the 20%

and 80% points.

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the 20%

and 80% points.

Voltage Overdrive Difference between the differential input and reference input voltages.

Data Sheet ADCMP561/ADCMP562

Rev. B | Page 11 of 14

APPLICATIONS INFORMATION

The ADCMP561/ADCMP562 comparators are very high speed

devices. Consequently, high speed design techniques must be

employed to achieve the best performance. The most critical

aspect of any ADCMP561/ADCMP562 design is the use of a low

impedance ground plane. A ground plane, as part of a multi-

layer board, is recommended for proper high speed performance.

Using a continuous conductive plane over the surface of the

circuit board can create this, allowing breaks in the plane only

for necessary signal paths. The ground plane provides a low

inductance ground, eliminating any potential differences at

different ground points throughout the circuit board caused by

ground bounce. A proper ground plane also minimizes the

effects of stray capacitance on the circuit board.

It is also important to provide bypass capacitors for the power

supply in a high speed application. A 1 µF electrolytic bypass

capacitor should be placed within 0.5 inches of each power

supply pin to ground. These capacitors reduce any potential

voltage ripples from the power supply. In addition, a 10 nF

ceramic capacitor should be placed as close as possible from the

power supply pins on the ADCMP561/ADCMP562 to ground.

These capacitors act as a charge reservoir for the device during

high frequency switching.

The LATCH ENABLE input is active low (latched). If the

latching function is not used, the LATCH ENABLE input may

be left open or may be attached to V

is a PECL logic

high). The complementary input,

LATCH ENABLE

, may be left

open or may be tied to V

− 2.0 V. Leaving the latch inputs

unconnected or providing the proper voltages disables the

latching function.

Occasionally, one of the two comparator stages within the

ADCMP561/ADCMP562 is not used. The inputs of the unused

comparator should not be allowed to float. The high internal

gain may cause the output to oscillate (possibly affecting the

comparator that is being used) unless the output is forced into a

fixed state. This is easily accomplished by ensuring that the two

inputs are at least one diode drop apart, while also appropriately

connecting the LATCH ENABLE and

LATCH ENABLE

inputs

as described previously.

The best performance is achieved with the use of proper PECL

terminations. The open emitter outputs of the ADCMP561/

ADCMP562 are designed to be terminated through 50 Ω

resistors to V

− 2.0 V, or any other equivalent PECL termina-

tion. If high speed PECL signals must be routed more than a

centimeter, microstrip or stripline techniques may be required

to ensure proper transition times and prevent output ringing.

CLOCK TIMING RECOVERY

Comparators are often used in digital systems to recover clock

timing signals. High speed square waves transmitted over a

distance, even tens of centimeters, can become distorted due to

stray capacitance and inductance. Poor layout or improper

termination can also cause reflections on the transmission line,

further distorting the signal waveform. A high speed comparator

can be used to recover the distorted waveform while maintaining a

minimum of delay.

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator amplifier, proper design

and layout techniques should be used to ensure optimal perfor-

mance from the ADCMP561/ADCMP562. The performance

limits of high speed circuitry can be a result of stray capaci-

tance, improper ground impedance, or other layout issues.

Minimizing resistance from source to the input is an important

consideration in maximizing the high speed operation of the

ADCMP561/ADCMP562. Source resistance in combination

with equivalent input capacitance could cause a lagged response

at the input, thus delaying the output. The input capacitance of

the ADCMP561/ADCMP562, in combination with stray capaci-

tance from an input pin to ground, could result in several

picofarads of equivalent capacitance. A combination of 3 kΩ

source resistance and 5 pF of input capacitance yields a time

constant of 15 ns, which is significantly slower than the 750 ps

capability of the ADCMP561/ADCMP562. Source impedances

should be significantly less than 100 Ω for best performance.

Sockets should be avoided due to stray capacitance and induct-

ance. If proper high speed techniques are used, the devices

should be free from oscillation when the comparator input

signal passes through the switching threshold.

COMPARATOR PROPAGATION DELAY

DISPERSION

The ADCMP561/ADCMP562 have been specifically designed

to reduce propagation delay dispersion over an input overdrive

range of 100 mV to 1.5 V. Propagation delay overdrive dispersion

is the change in propagation delay that results from a change in

the degree of overdrive (how far the switching point is exceeded

by the input). The overall result is a higher degree of timing

accuracy because the ADCMP561/ADCMP562 are far less

sensitive to input variations than most comparator designs.

ADCMP561/ADCMP562 Data Sheet

Rev. B | Page 12 of 14

Propagation delay dispersion is a specification that is important

in critical timing applications such as ATE, bench instruments,

and nuclear instrumentation. Overdrive dispersion is defined

as the variation in propagation delay as the input overdrive

conditions are changed (Figure 19). For the ADCMP561 and

ADCMP562, overdrive dispersion is typically 75 ps as the

overdrive is changed from 100 mV to 1.5 V. This specification

applies for both positive and negative overdrive because the

ADCMP561/ADCMP562 have equal delays for positive and

negative going inputs.

Q OUTPUT

INPUT VOLTAGE

1.5V OVERDRIVE

20mV OVERDRIVE

DISPERSION

REF

± V

04687-0-005

Figure 19. Propagation Delay Dispersion

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often useful in a

noisy environment, or where it is not desirable for the compara-

tor to toggle between states when the input signal is at the

switching threshold. The transfer function for a comparator

with hysteresis is shown in Figure 20. If the input voltage

approaches the threshold from the negative direction, the

comparator switches from a 0 to a 1 when the input crosses

/2. The new switching threshold becomes −V

/2. The

comparator remains in a 1 state until the threshold −V

/2 is

crossed, coming from the positive direction. In this manner,

noise centered on 0 V input does not cause the comparator to

switch states unless it exceeds the region bounded by ±V

/2.

Positive feedback from the output to the input is often used to

produce hysteresis in a comparator (Figure 24). The major

problem with this approach is that the amount of hysteresis

varies with the output logic levels, resulting in a hysteresis that

is not symmetrical around zero.

In the ADCMP562, hysteresis is generated through the

programmable hysteresis pin. A resistor from the HYS pin to

GND creates a current into the part that is used to generate

hysteresis. Hysteresis generated in this manner is independent

of output swing and is symmetrical around the trip point. The

hysteresis versus resistance curve is shown in Figure 21.

A current source can also be used with the HYS pin. The

relationship between the current applied to the HYS pin and the

resulting hysteresis is shown in Figure 17.

OUTPUT

INPUT

–V

04687-0-006

Figure 20. Comparator Hysteresis Transfer Function

160

140

120

100

010

20304050

04687-0-021

HYS

(kΩ)

PROGRAMMED HYSTERESIS (mV)

Figure 21. Comparator Hysteresis vs. R

HYS

MINIMUM INPUT SLEW RATE REQUIREMENT

As for all high speed comparators, a minimum slew rate must

be met to ensure that the device does not oscillate when the

input crosses the threshold. This oscillation is due in part to the

high input bandwidth of the comparator and the parasitics of

the package. Analog Devices recommends a slew rate of 1 V/µs

or faster to ensure a clean output transition. If slew rates less

than 1 V/µs are used, hysteresis should be added to reduce the

oscillation.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

ADCMP562BRQ

Mfr. #:

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Description:

Analog Comparators Dual - Supply High Speed PECL

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ADCMP562BRQ

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