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MAX13206EELA+T

P1-P3P4-P6P7-P9
Detailed Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are diode arrays designed to protect sensitive electron-
ics against damage resulting from ESD conditions or
transient voltages. The low input capacitance makes
these devices ideal for high-speed data lines. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E
protect two, four, six, and eight channels, respectively.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are designed to work in conjunction with a device’s
intrinsic ESD protection. The MAX13202E/MAX13204E/
MAX13206E/MAX13208E limit the excursion of the ESD
event to below ±25V peak voltage when subjected to the
Human Body Model waveform. When subjected to the
IEC 61000-4-2 waveform, the peak voltage is limited to
±80V (Contact Discharge) and ±120V (Air-Gap
Discharge). The device that is being protected by the
MAX13202E/MAX13204E/ MAX13206E/MAX13208E
must be able to withstand these peak voltages plus any
additional voltage generated by the parasitic board.
Applications Information
Design Considerations
Maximum protection against ESD damage results from
proper board layout (see the Layout Recommendations
section and Figure 2). A good layout reduces the para-
sitic series inductance on the ground line, supply line,
and protected signal lines.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
V
CC
. In an ideal circuit, the clamping voltage, V
C
, is
defined as the forward voltage drop, V
F
, of the protection
diode plus any supply voltage present on the cathode.
For positive ESD pulses:
V
C
= V
CC
+ V
F
For negative ESD pulses:
V
C
= -V
F
In reality, the effect of the parasitic series inductance
on the lines must also be considered (Figure 1).
For positive ESD pulses:
For negative ESD pulses:
where I
ESD
is the ESD current pulse.
VV Lx
dI
dt
Lx
dI
dt
CFD
ESD ESD
()
()
=− +
+
()
2
13
VV V Lx
dI
dt
Lx
dI
dt
CCCFD
ESD ESD
()
()
=+ +
+
()
1
12
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
4 _______________________________________________________________________________________
L1
PROTECTED
LINE
L3
D2
GROUND RAIL
POSITIVE SUPPLY RAIL
I/O_
D1
L2
Figure 1. Parasitic Series Inductance
V
CC
PROTECTED LINE
NEGATIVE ESD
CURRENT
PULSE
PATH TO
GROUND
PROTECTED
CIRCUIT
GND
D1
I/O_
V
C
D2
L1
L3
L2
Figure 2. Layout Considerations
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
_______________________________________________________________________________________ 5
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 3). For example,
in a ±15kV IEC-61000-4-2 Air-Gap Discharge ESD
event, the pulse current rises to approximately 45A in
1ns (di/dt = 45 x 10
9
). An inductance of only 10nH adds
an additional 450V to the clamp voltage. An inductance
of 10nH represents approximately 0.5in of board trace.
Regardless of the device’s specified diode clamp volt-
age, a poor layout with parasitic inductance significantly
increases the effective clamp voltage at the protected
signal line.
A low-ESR 0.1µF capacitor must be used between V
CC
and GND. This bypass capacitor absorbs the charge
transferred by a +14kV (MAX13204E/MAX13206E/
MAX13208E) and ±12kV (MAX13202E) IEC61000-4-2
Contact Discharge ESD event.
Ideally, the supply rail (V
CC
) would absorb the charge
caused by a positive ESD strike without changing its
regulated value. In reality, all power supplies have an
effective output impedance on their positive rails. If a
power supply’s effective output impedance is 1Ω, then
by using V = I × R, the clamping voltage of V
C
increas-
es by the equation V
C
= I
ESD
x R
OUT
. An ±8kV
IEC 61000-4-2 ESD event generates a current spike of
24A, so the clamping voltage increases by V
C
= 24A ×
1Ω, or V
C
= 24V. Again, a poor layout without proper
bypassing increases the clamping voltage. A ceramic
chip capacitor mounted as close to the MAX13202E/
MAX13204E/MAX13206E/MAX13208E V
CC
pin is the
best choice for this application. A bypass capacitor
should also be placed as close to the protected device
as possible.
±30kV ESD Protection
ESD protection can be tested in various ways. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E are
characterized for protection to the following limits:
•±15kV using the Human Body Model
•±14kV (MAX13204E/MAX13206E/MAX13208E) and
±12kV (MAX13202E) using the Contact Discharge
method specified in IEC 61000-4-2
•±30kV using the IEC 61000-4-2 Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
C
s
100pF
R
C
1MΩ
R
D
1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 4. Human Body ESD Test Model
I
P
100%
90%
36.8%
t
RL
TIME
t
DL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
10%
0
0
AMPERES
Figure 5. Human Body Model Current Waveform
t
R
= 0.7ns to 1ns
30ns
60ns
t
100%
90%
10%
I
PEAK
I
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
MAX13202E/MAX13204E/MAX13206E/MAX13208E
Human Body Model
Figure 4 shows the Human Body Model, and Figure 5
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩ resistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. The MAX13202E/
MAX13204E/MAX13206E/MAX13208E help users
design equipment that meets Level 4 of IEC 61000-4-2.
The main difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2. Because series resistance is
lower in the IEC 61000-4-2 ESD test model (Figure 6),
the ESD-withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 3 shows the current waveform for
the ±8kV IEC 61000-4-2 Level 4 ESD Contact
Discharge test.
The Air-Gap Discharge test involves approaching the
device with a charged probe. The Contact Discharge
method connects the probe to the device before the
probe is energized.
Layout Recommendations
Proper circuit-board layout is critical to suppress ESD-
induced line transients. The MAX13202E/MAX13204E/
MAX13206E/MAX13208E clamp to ±120V; however, with
improper layout, the voltage spike at the device is much
higher. A lead inductance of 10nH with a 45A current
spike at a dv/dt of 1ns results in an ADDITIONAL 450V
spike on the protected line. It is essential that the layout
of the PC board follows these guidelines:
1) Minimize trace length between the connector or
input terminal, I/O_, and the protected signal line.
2) Use separate planes for power and ground to reduce
parasitic inductance and to reduce the impedance to
the power rails for shunted ESD current.
3) Ensure short ESD transient return paths to GND
and V
CC
.
4) Minimize conductive power and ground loops.
5) Do not place critical signals near the edge of the
PC board.
6) Bypass V
CC
to GND with a low-ESR ceramic capaci-
tor as close to V
CC
and ground terminals as possible.
7) Bypass the supply of the protected device to GND
with a low-ESR ceramic capacitor as close to the
supply pin as possible.
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
6 _______________________________________________________________________________________
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
C
s
150pF
R
C
50Ω to 100Ω
R
D
330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 6. IEC 61000-4-2 ESD Test Model
Chip Information
PROCESS: BiCMOS
P1-P3P4-P6P7-P9

MAX13206EELA+T

Mfr. #:
Buy MAX13206EELA+T
Manufacturer:
Maxim Integrated
Description:
ESD Suppressors / TVS Diodes 6Ch ESD Protection Diode Array
Lifecycle:
New from this manufacturer.
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