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IS62WV5128DALL-55T2LI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
IS62WV5128DALL/DBLL
IS65WV5128DALL/DBLL
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
11/01/2016
®
Long-term Support
World Class Quality
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
35ns 45ns 55 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC WriteCycleTime 35 — 45 — 55 —  ns
tSCS1 CS1toWriteEnd 25 — 35 — 45 —  ns
tAW AddressSetupTimetoWriteEnd 25 — 35 — 45 —  ns
thA AddressHoldfromWriteEnd 0 — 0 — 0 — ns
tSA AddressSetupTime 0 — 0 — 0 — ns
tPWe WEPulseWidth 25 — 35 — 40 — ns
tSd DataSetuptoWriteEnd 20 — 20 — 25 —  ns
thd DataHoldfromWriteEnd 0 — 0 — 0 — ns
thzWe
(3)
WELOWtoHigh-ZOutput — 10 — 20 — 20 ns
tLzWe
(3)
WEHIGHtoLow-ZOutput 3 — 5 — 5 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4Vto
V
dd-0.2V/Vdd-0.3VandoutputloadingspeciedinFigure1.
2. TheinternalwritetimeisdenedbytheoverlapofCS1LOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling
edge of the signal that terminates the write.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE=HIGHorLOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
tPWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
WE
DOUT
DIN
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. A1
11/01/2016
IS62WV5128DALL/DBLL
IS65WV5128DALL/DBLL
®
Long-term Support
World Class Quality
WRITE CYCLE NO. 2 (WE Controlled: OEisHIGHDuringWriteCycle)
WRITE CYCLE NO. 3 (WE Controlled: OEisLOWDuringWriteCycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
WE
DOUT
DIN
DATA-IN VALID
DATA UNDEFINED
t
WC
tSCS1
tAW
tHA
t
PWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
WE
DOUT
DIN
IS62WV5128DALL/DBLL
IS65WV5128DALL/DBLL
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
11/01/2016
®
Long-term Support
World Class Quality
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VdrVddforDataRetention SeeDataRetentionWaveform 1.2 3.6 V
Idr DataRetentionCurrent Vdd=1.2V,CS1 ≥Vdd –0.2V Com. — 3 µA
Ind. — 7
Auto. — 20
typ.
(1)
1
tSdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — ns
trdr RecoveryTime SeeDataRetentionWaveform trC — ns
Note: 1.TypicalvaluesaremeasuredatVdd=3.0V,TA=25
o
Candnot100%tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
V
DD
CS1 ≥ V
DD
-
0.2V
t
SDR
t
RDR
V
DR
CS1
GND
Data Retention Mode
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

IS62WV5128DALL-55T2LI

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IC SRAM 4M PARALLEL 32TSOP II
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