LTC1745CFW#TRPBF Datasheet LTC1745CFW#PBF, LTC1745CFW#TRPBF, LTC1745IFW#TRPBF | P16-P18

LTC1745

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Any noise present on the encode signal will result in

additional aperture jitter that will be RMS summed with the

inherent ADC aperture jitter.

In applications where jitter is critical (high input frequen-

cies) take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude as possible; if transformer

coupled use a higher turns ratio to increase the

amplitude.

3. If the ADC is clocked with a sinusoidal signal, filter the

encode signal to reduce wideband noise.

4. Balance the capacitance and series resistance at both

encode inputs so that any coupled noise will appear at

both inputs as common mode noise.

The encode inputs have a common mode range of 1.8V to

. Each input may be driven from ground to V

for

single-ended drive.

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC1745 is 25Msps. For

the ADC to operate properly the encode signal should have

a 50% (±5%) duty cycle. Each half cycle must have at least

19ns for the ADC internal circuitry to have enough settling

time for proper operation. Achieving a precise 50% duty

cycle is easy with differential sinusoidal drive using a

transformer or using symmetric differential logic such as

PECL or LVDS. When using a single-ended encode signal

asymmetric rise and fall times can result in duty cycles that

are far from 50%.

At sample rates slower than 25Msps the duty cycle can

vary from 50% as long as each half cycle is at least 19ns.

The lower limit of the LTC1745 sample rate is determined

by the droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals

on small valued capacitors. Junction leakage will dis-

charge the capacitors. The specified minimum operating

frequency for the LTC1745 is 1Msps.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OV

and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50Ω to external

circuitry and may eliminate the need for external damping

resistors.

LTC1745

1745 F09

0.1µF

43Ω

TYPICAL

DATA

OUTPUT

OGND

0.5V TO

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 9. Equivalent Circuit for a Digital Output Buffer

LTC1745

1745f

Output Loading

As with all high speed/high resolution converters the

digital output loading can affect the performance. The

digital outputs of the LTC1745 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

output may be used but is not required since the ADC has

a series resistor of 43Ω on chip.

Lower OV

voltages will also help reduce interference

from the digital outputs.

Format

The LTC1745 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MSBINV pin; high selects offset binary.

Overflow Bit

An overflow output bit indicates when the converter is

overranged or underranged. When OF outputs a logic high

the converter is either overranged or underranged.

Output Clock

The ADC has a delayed version of the ENC input available

as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system.

This is necessary when using a sinusoidal encode. Data

will be updated just after CLKOUT falls and can be latched

on the rising edge of CLKOUT.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OV

, should be tied

to the same power supply as for the logic being driven. For

example if the converter is driving a DSP powered by a 3V

supply then OV

should be tied to that same 3V supply.

can be powered with any voltage up to 5V. The logic

outputs will swing between OGND and OV

Output Enable

The outputs may be disabled with the output enable pin,

OE. OE high disables all data outputs including OF and

CLKOUT. The data access and bus relinquish times are too

slow to allow the outputs to be enabled and disabled

during full speed operation. The output Hi-Z state is

intended for use during long periods of inactivity.

GROUNDING AND BYPASSING

The LTC1745 requires a printed circuit board with a clean

unbroken ground plane. A multilayer board with an inter-

nal ground plane is recommended. The pinout of the

LTC1745 has been optimized for a flowthrough layout so

that the interaction between inputs and digital outputs is

minimized. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track or

underneath the ADC.

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LTC1745

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APPLICATIO S I FOR ATIO

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High quality ceramic bypass capacitors should be used at

the V

DD,

, REFHA, REFHB, REFLA and REFLB pins as

shown in the block diagram on the front page of this data

sheet. Bypass capacitors must be located as close to the

pins as possible. Of particular importance are the capaci-

tors between REFHA and REFLB and between REFHB and

REFLA. These capacitors should be as close to the device

as possible (1.5mm or less). Size 0402 ceramic capacitors

are recomended. The large 4.7µF capacitor between REFHA

and REFLA can be somewhat further away. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The LTC1745 differential inputs should run parallel and

close to each other. The input traces should be as short as

possible to minimize capacitance and to minimize noise

pickup.

An analog ground plane separate from the digital process-

ing system ground should be used. All ADC ground pins

labeled GND should connect to this plane. All ADC V

bypass capacitors, reference bypass capacitors and input

filter capacitors should connect to this analog plane. The

LTC1745 has three output driver ground pins, labeled

OGND (Pins 27, 38 and 47). These grounds should con-

nect to the digital processing system ground. The output

driver supply, OV

should be connected to the digital

processing system supply. OV

bypass capacitors should

bypass to the digital system ground. The digital process-

ing system ground should be connected to the analog

plane at ADC OGND (Pin 38).

HEAT TRANSFER

Most of the heat generated by the LTC1745 is transferred

from the die through the package leads onto the printed

circuit board. In particular, ground pins 12, 13, 36 and 37

are fused to the die attach pad. These pins have the lowest

thermal resistance between the die and the outside envi-

ronment. It is critical that all ground pins are connected to

a ground plane of sufficient area. The layout of the evalu-

ation circuit shown on the following pages has a low ther-

mal resistance path to the internal ground plane by using

multiple vias near the ground pins. A ground plane of this

size results in a thermal resistance from the die to ambient

of 35°C/W. Smaller area ground planes or poorly connected

ground pins will result in higher thermal resistance.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC1745CFW#TRPBF

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Analog to Digital Converters - ADC 12-bit, 25Msps Low Power ADC

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