74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 5 of 18
NXP Semiconductors
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
5.2 Pin description
6. Functional description
6.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
Z = high-impedance OFF-state.
Table 2. Pin description
Symbol Pin Description
1OE
, 2OE 1, 24 output enable input (active LOW)
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data outputs
2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data outputs
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
V
CC
7, 18, 31, 42 positive supply voltage
1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs
2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs
1LE, 2LE 48, 25 latch enable input (active HIGH)
Table 3. Function table
[1]
Inputs Internal latches Outputs nQn Operating mode
nOE nLE nDn
L H L L L enable and read register
(transparent mode)
LHHH H
L L l L L latch and read register
(hold mode)
LLhH H
H L l L Z latch register and disable outputs
HLhH Z
