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AD8572AR-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
AD8571/AD8572/AD8574 Data Sheet
Rev. F | Page 16 of 28
AUTO-ZERO PHASE
In this phase, all ΦA
X
switches are closed, and all ΦB switches
are open. Here, the nulling amplifier is taken out of the gain
loop by shorting its two inputs together. Of course, there is a
degree of offset voltage, shown as V
OSA
, inherent in the nulling
amplifier, that maintains a potential difference between the +IN
and −IN inputs. The nulling amplifier feedback loop is closed
through ΦA
2
, and V
OSA
appears at the output of the nulling
amplifier and on C
M1
, an internal capacitor in the AD8571/
AD8572/AD8574. Mathematically, this can be expressed in the
time domain as
V
OA
[t] = A
A
V
OSA
[t] − B
A
V
OA
[t] (1)
This can also be expressed as
[ ]
[ ]
A
OSAA
OA
B
tVA
tV
+
=
1
(2)
The previous equations show that the offset voltage of the nulling
amplifier times a gain factor appears at the output of the nulling
amplifier and thus on the C
M1
capacitor.
AMPLIFICATION PHASE
When the ΦB switches close and the ΦA
X
switches open for
the amplification phase, the offset voltage remains on CM1 and
essentially corrects any error from the nulling amplifier. The
voltage across C
M1
is designated as V
NA
. The potential difference
between the two inputs to the primary amplifier is designated as
V
IN
, or V
IN
= (V
IN+
− V
IN−
). The output of the nulling amplifier
can then be expressed as
V
OA
[t] = A
A
(V
IN
[t] − V
OSA
[t]) − B
A
V
NA
[t] (3)
Because ΦA
X
is now open and there is no place for C
M1
to
discharge, the voltage (V
NA
) at the present time (t) is equal to
the voltage at the output of the nulling amp (V
OA
) at the time when
ΦA
X
is closed. If the period of the autocorrection switching
frequency is designated as T
S
, the amplifier switches between
phases every 0.5 × T
S
. Therefore, in the amplification phase
[
]
−=
SNA
NA
TtV
tV
2
1
(4)
and substituting Equation 4 and Equation 2 into Equation 3 yields
[ ] [ ] [ ]
A
S
OSAAA
OSAA
IN
AOA
B
TtVBA
tV
AtVAtV
+
−
−+=
1
2
1
(5)
For the sake of simplification, it can be assumed that the auto-
correction frequency is much faster than any potential change
in V
OSA
or V
OSB
. This is a good assumption because changes in
offset voltage are a function of temperature variation or long-
term wear time, both of which are much slower than the
auto-zero clock frequency of the AD8571/AD8572/AD8574,
which effectively makes the V
OS
time invariant, and Equation 5
can be rewritten as
[
] [
]
( )
A
OSAAAOSAAA
IN
AOA
B
VBAVBA
t
VA
t
V
+
−+
+=
1
1
(6)
or
[ ] [ ]
+
+=
A
OSA
IN
AOA
B
V
tVAtV
1
(7)
Here, the auto-zeroing becomes apparent. Note that the V
OS
term is reduced by a factor of 1 + B
A
, which shows how the
nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Therefore, the
primary amplifier output voltage is the voltage at the output of the
AD8571/AD8572/AD8574 amplifier. It is equal to
V
OUT
[t] = A
B
(V
IN
[t] + V
OSB
) + B
B
V
NB
(8)
In the amplification phase, V
OA
= V
NB
, so this can be rewritten as
[ ]
[ ]
[
]
+
+++
=
A
OSA
IN
A
B
OSB
BINB
OUT
B
V
t
VA
BVAtV
A
t
V
1
(9)
Combining terms yield
[ ]
[ ]
( )
OSB
B
A
OSA
B
A
B
A
BIN
OUT
VA
B
VBA
BAAtV
tV
+
+
++
=
1
(10)
The AD8571/AD8572/AD8574 architecture is optimized in
such a way that A
A
= A
B
, B
A
= B
B
, and B
A
>> 1. In addition, the
gain product to A
A
B
B
is much greater than A
B
. Therefore,
Equation 10 can be simplified to
V
OUT
[t] = V
IN
[t]A
A
B
A
+ A
A
(V
OSA
+ V
OSB
) (11)
Most obvious is the gain product of both the primary and nulling
amplifiers. This A
A
B
A
term is what gives the AD8571/AD8572/
AD8574 extremely high open-loop gain. To understand how
V
OSA
and V
OSB
relate to the overall effective input offset voltage of
the complete amplifier, set up the generic amplifier equation of
V
OUT
= k × (V
IN
+ V
OS, EFF
) (12)
where:
k is the open-loop gain of an amplifier.
V
OS, EFF
is its effective offset voltage.
Putting Equation 12 into the form of Equation 11 gives
V
OUT
[t] = V
IN
[t]A
A
B
A
+ V
OS, EFF
A
A
B
A
(13)
Data Sheet AD8571/AD8572/AD8574
Rev. F | Page 17 of 28
Therefore,
A
OSB
OSA
EFF
OS
B
VV
V
+
≈
,
(14)
Thus, the offset voltages of both the primary and nulling ampli-
fiers are reduced by the gain factor B
A
, which takes a typical input
offset voltage from several millivolts down to an effective input
offset voltage of submicrovolts. This autocorrection scheme makes
the AD8571/AD8572/AD8574 amplifiers extremely precise.
HIGH GAIN, CMRR, AND PSRR
Common-mode and power supply rejection are indications of the
amount of offset voltage an amplifier has as a result of a change in
its input common-mode or power supply voltages. As shown in
the Amplification Phase section, the autocorrection architecture
of the AD8571/AD8572/AD8574 allows it to effectively
minimize offset voltages. The technique also corrects for offset
errors caused by common-mode voltage swings and power
supply variations, which results in superb CMRR and PSRR
figures in excess of 130 dB. Because the autocorrection occurs
continuously, these figures can be maintained across the
temperature range of the device (−40°C to +125°C).
MAXIMIZING PERFORMANCE THROUGH PROPER
LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD8571/AD8572/
AD8574, care should be taken in the circuit board layout. The
PCB surface must remain clean and free of moisture to avoid
leakage currents between adjacent traces. Surface coating of the
circuit board reduces surface moisture and provides a humidity
barrier, reducing parasitic resistance on the board. The use of
guard rings around the amplifier inputs further reduces leakage
currents. Figure 52 shows how the guard ring should be config-
ured, and Figure 53 shows the top view of how a surface-mount
layout can be arranged. The guard ring does not need to be a
specific width, but it should form a continuous loop around both
inputs. By setting the guard ring voltage equal to the voltage at
the non-inverting input, parasitic capacitance is minimized as
well. For further reduction of leakage currents, components can be
mounted to the PCB using Teflon® standoff insulators.
V
OUT
V
OUT
V
OUT
V
IN
AD8572
V
IN
AD8572
V
IN
AD8572
01104-052
Figure 52. Guard Ring Layout and Connections to
Reduce PCB Leakage Currents
V–
V+
V
REF
V
REF
V
IN1
V
IN2
GUARD
RING
R1 R2
R2 R1
AD8572
GUARD
RING
01104-053
Figure 53. Top View of AD8572 SOIC Layout with Guard Rings
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the junction temperature. The most common
metallic junctions on a circuit board are solder-to-board trace
and solder-to-component lead. Figure 54 shows a cross-section
view of the thermal voltage error sources. When the temperature
of the PCB at one end of the component (T
A1
) differs from the
temperature at the other end (T
A2
), the Seebeck voltages are not
equal, resulting in a thermal voltage error.
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
that both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on the
circuit board further reduces this error. The use of a ground
plane helps distribute heat throughout the board and also
reduces EMI noise pickup.
SURFACE MOUNT
COMPONENT
COMPONENT
LEAD
SOLDER
PC BOARD
COPPER
TRACE
T
A2
IF T
A1
≠
T
A2
, THEN
V
TS1 +
V
SC1
≠ V
TS2 +
V
SC2
T
A1
V
SC1
V
TS1
+
–
+
–
V
SC2
V
TS2
+
+
–
–
01104-054
Figure 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error
R
S
SHOULD BE PLACED IN CLOSE PROXIMITY AND
ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES
V
OUT
V
IN
AD8571/AD8572/
AD8574
A
V
= 1 + (R
F
/R1)
R
F
R
S
= R1
R1
01104-055
Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors
AD8571/AD8572/AD8574 Data Sheet
Rev. F | Page 18 of 28
1/f NOISE CHARACTERISTICS
Another advantage of auto-zero amplifiers is their ability to
cancel flicker noise. Flicker noise, also known as 1/f noise, is
noise inherent in the physics of semiconductor devices and
increases 3 dB for every octave decrease in frequency. The 1/f
corner frequency of an amplifier is the frequency at which the
flicker noise is equal to the broadband noise of the amplifier.
At lower frequencies, flicker noise dominates, causing higher
degrees of error for sub-Hertz frequencies or dc precision
applications.
Because the AD8571/AD8572/AD8574 amplifiers are self-
correcting op amps, they do not have increasing flicker noise at
lower frequencies. In essence, low frequency noise is treated as a
slowly varying offset error and is greatly reduced with
autocorrection. The correction becomes more effective as the
noise frequency approaches dc, offsetting the tendency of the
noise to increase exponentially as frequency decreases, which
allows the AD8571/AD8572/AD8574 to have lower noise near
dc than standard low noise amplifiers that are susceptible to 1/f
noise.
RANDOM AUTO-ZERO CORRECTION ELIMINATES
INTERMODULATION DISTORTION
The AD8571/AD8572/AD8574 can be used as conventional
op amps for gains up to 1 MHz. The auto-zero correction
frequency of the device continuously varies, based on a
pseudorandom generator with a uniform distribution from
2 kHz to 4 kHz. The randomization of the autocorrection clock
creates a continuous randomization of IMD products that show
up as simple broadband noise at the output of the amplifier. This
broadband noise naturally combines with the amplifier voltage
noise in a root-squared-sum fashion, resulting in an output free
IMD. Figure 56 shows the spectral output of an AD8572 with
the amplifier configured for unity gain and the input grounded.
Figure 57 shows the spectral output with the amplifier
configured for a gain of 60 dB.
01104-056
0
–20
–40
–80
–60
–120
–140
–100
–160
1 2 3 4 5
6 7 8 9 10
OUTPUT SIGNAL
FREQUENCY (kHz)
V
S
= 5V
A
V
= 0dB
Figure 56. Spectral Analysis of AD8572 Output in Unity Gain Configuration
0
–20
–40
–60
–80
–100
–120
0 1 2 3 4 5 6 7 8
9 10
01104-057
OUTPUT SIGNAL
FREQUENCY (kHz)
V
S
= 5V
A
V
= 60dB
Figure 57. Spectral Analysis of AD8571/AD8572/AD8574 Output
with 60 dB Gain
Figure 58 shows the spectral output of an AD8572 configured in
a high gain (60 dB) with a 1 mV input signal applied. Note the
absence of any IMD products in the spectrum. The signal-to-
noise ratio (SNR) of the output signal is better than 60 dB, or 0.1%.
0
–20
–40
–60
–80
–100
–120
0 1
2 3 4 5 6 7 8 9
10
01104-058
V
S
= 5V
A
V
= 60dB
FREQUENCY (kHz)
OUTPUT SIGNAL
Figure 58. Spectral Analysis of AD8572 in High Gain with an Input Signal
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AD8572AR-REEL

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Operational Amplifiers - Op Amps Zero-Drft SGL-Supply RRIO Dual
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