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L6387ED013TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
DocID13990 Rev 4 7/17
L6387E Electrical characteristics
17
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
Logic inputs
V
il
1, 2
Low level logic threshold voltage 1.5 V
V
ih
High level logic threshold voltage 3.6 V
I
ih
High level logic input current V
IN
= 15 V 50 70 µA
I
il
Low level logic input current V
IN
= 0 V 1 µA
1. R
DS(on)
is tested in the following way:
where I
1
is the pin 8 current when V
BOOT
= V
BOOT1
, I
2
when V
BOOT
= V
BOOT2
.
Table 6. DC operation electrical characteristics (continued) (V
CC
= 15 V; T
J
= 25 °C)
R
DSON
V
CC
V
BOOT1
–V
CC
V
BOOT2
––
I
1
V
CC
,V
BOOT1
I
2
V
CC
,V
BOOT2
–
-----------------------------------------------------------------------------------------------=
Input logic L6387E
8/17 DocID13990 Rev 4
5 Input logic
L6387E input logic is V
CC
(17 V) compatible. An interlocking feature is offered (seeTable 7)
to avoid undesired simultaneous turn-ON of both power switches driven.
Table 7. Input logic
Input Output
HIN LIN HVG LVG
000 0
010 1
101 0
110 0
DocID13990 Rev 4 9/17
L6387E Bootstrap driver
17
6 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 3 a). In the L6387E device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as
shown in Figure 3 b. An internal charge pump (Figure 3 b) provides the DMOS driving
voltage. The diode connected in series to the DMOS has been added to avoid undesirable
turn-on.
C
BOOT
selection and charging
To choose the proper C
BOOT
value, the external MOSFET can be seen as an equivalent
capacitor. This capacitor C
EXT
is related to the MOSFET total gate charge:
Equation 1
The ratio between the C
EXT
and C
BOOT
capacitors is proportional to the cyclical voltage loss.
It has to be:
C
BOOT
>>>C
EXT
E.g.: if Q
gate
is 30 nC and V
gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the C
BOOT
selection has to take into account also
the leakage losses.
E.g.: HVG steady state consumption is lower than 100 A, so if HVG T
ON
is 5 ms, C
BOOT
has to supply a maximum of 0.5 µC to C
EXT
. This charge on a 1 F capacitor means
a voltage drop of 0.5 V.
The internal bootstrap driver gives great advantages: the external fast recovery diode can
be avoided (it usually has a great leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (T
charge
) of the C
BOOT
is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DSON
(typical value:
125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken into account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 2
where Q
gate
is the gate charge of the external power MOSFET, R
dson
is the on-resistance of
the bootstrap DMOS, and T
charge
is the charging time of the bootstrap capacitor.
C
EXT
Q
gate
V
gate
-------------- -=
V
drop
I
ch earg
R
dson
V
drop
Q
gate
T
ch earg
------------------- R
dson
==
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

L6387ED013TR

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Manufacturer:
STMicroelectronics
Description:
Gate Drivers HV H-Bridge driver
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