1. General description
The 74AHC125-Q100; 74AHCT125-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard JESD7-A.
The 74AHC125-Q100; 74AHCT125-Q100 provides four non-inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input
(nOE
). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125-Q100; 74AHCT125-Q100 is identical to the 74AHC126-Q100;
74AHCT126-Q100 but has active LOW enable inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt trigger action
Inputs accept voltages higher than V
CC
For 74AHC125-Q100: CMOS input levels
For 74AHCT125-Q100: TTL input levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Multiple package options
74AHC125-Q100;
74AHCT125-Q100
Quad buffer/line driver; 3-state
Rev. 1 — 5 June 2012 Product data sheet
