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dc1658afb
DEMO MANUAL DC1658A
operating principle
Refer to the block diagram within the LTC3388-1/
LTC3388-3 data sheet for its operating principle.
The LTC3388
is an ultralow quiescent current power sup-
ply designed to regulate the output voltage by means of a
nanopower high efficiency synchronous buck regulator
. See
Figure 1 for the LTC3588-1 50mA efficiency versus input
voltage curves for the four output voltage settings. Figure
2 is the efficiency curves for the LTC3588-3. The input
current is only 720nA typical at no load while maintaining
output voltage regulation capable of supplying 50mA of
load current.
The LTC3388-1/LTC3388-3 also incorporates an accurate
undervoltage lockout feature to disable the converter and
maintain a low quiescent current (approximately 400nA),
state when the input voltage falls below 2.3V. When the
voltage on V
IN
rises above the UVLO rising threshold, the
buck converter is enabled and charge is transferred from
the input capacitor to the output capacitor.
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
V
OUT
sense pin. The buck converter charges the output
capacitor through an inductor to a value slightly higher
than the regulation point. It does this by ramping the
inductor current up to 150mA through an internal PMOS
switch and then ramping down to 0mA through an internal
NMOS switch. When the buck converter brings the output
voltage into regulation, the LTC3388-1/LTC3388-3 enter
a sleep state in which both input and output quiescent
currents are minimal. The buck converter turns on and
off as needed to maintain regulation.
Two logic pins, EN and STBY, determine the operating mode
of the LTC3388-1/LTC3388-3. When EN is high and STBY
is low the synchronous buck converter is enabled and will
regulate the output if the input is above the programmed
output voltage and above the UVLO threshold. If EN is low,
the buck converter circuitry is powered to save quiescent
current. The internal rail generation circuits are kept alive
and the voltages at V
IN2
and CAP are maintained.
While enabled, the LTC3388-1/LTC3388-3 can be placed
in standby mode by bringing STBY high. In standby mode
the buck converter is disabled, eliminating the quiescent
current used to run the buck circuitry. The PGOOD and
sleep comparators are kept alive to maintain the state
of the PGOOD pin. The sleep comparator has a lower
quiescent current than the PGOOD comparator and when
the LTC3388-1/LTC3388-3 is in sleep mode, the PGOOD
comparator is shut down and PGOOD is held high. If
STBY is driven high with EN low, it will be ignored and
will remain in shutdown.
Four output voltages are available by tying the output
select pins, D0 and D1, to GND of V
IN2
. Table 1 shows
the four D0/D1 codes and their corresponding output
voltages with up to 50mA of continuous output current.
The internal feedback network draws a small amount of
current from V
OUT
.
A power good comparator produces a logic high ref-
erenced to V
OUT
on the PGOOD pin when the converter
reaches the programmed V
OUT
, signaling that the output
is in regulation. The PGOOD pin will remain Hi-Z until
V
OUT
falls below 92% of the desired regulation voltage.
IF PGOOD is high and V
IN
falls below the UVLO falling
threshold, PGOOD will remain high until V
OUT
falls to 92%
of the desired regulation point.
