NCP1587E
http://onsemi.com
10
P
IC
= control IC power dissipation,
I
CC
= IC measured supply current,
V
CC
= IC supply voltage,
P
TG
= top gate driver losses,
P
BG
= bottom gate driver losses.
The upper (switching) MOSFET gate driver losses are:
P
TG
+ Q
TG
f
SW
V
BST
Where:
Q
TG
= total upper MOSFET gate charge at VBST,
f
SW
= the switching frequency,
V
BST
= the BST pin voltage.
The lower (synchronous) MOSFET gate driver losses are:
P
BG
+ Q
BG
f
SW
V
CC
Where:
Q
BG
= total lower MOSFET gate charge at V
CC
.
The junction temperature of the control IC can then be
calculated as:
T
J
+ T
A
) P
IC
q
JA
Where:
T
J
= the junction temperature of the IC,
T
A
= the ambient temperature,
θ
JA
= the junction−to−ambient thermal resistance of the
IC package.
The package thermal resistance can be obtained from the
specifications section of this data sheet and a calculation can
be made to determine the IC junction temperature. However,
it should be noted that the physical layout of the board, the
proximity of other heat sources such as MOSFETs and
inductors, and the amount of metal connected to the IC,
impact the temperature of the device. Use these calculations
as a guide, but measurements should be taken in the actual
application.
Layout Considerations
As in any high frequency switching converter, layout is
very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. The figure below shows the critical power
components of the converter. To minimize the voltage
overshoot the interconnecting wires indicated by heavy lines
should be part of ground or power plane in a printed circuit
board. The components shown in the figure below should be
located as close together as possible. Please note that the
capacitors C
IN
and C
OUT
each represent numerous physical
capacitors. It is desirable to locate the NCP1587E within 1
inch of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the
NCP1587E must be sized to handle up to 2 A peak current.
Figure 12. Components to be Considered for
Layout Specifications
DESIGN EXAMPLE I: Type II Compensation
(Electrolytic Cap. with large ESR)
Switching Frequency F
SW
= 275 KHz
Output Capacitance R
ESR
= 45 mW/Each
Output Capacitance C
out
= 2×1800 mF
Output Inductance L
out
= 1 mH
Input Voltage V
in
= 12 V
Output Voltage V
out
= 1.6 V
Choose the loop gain crossover frequency;
F
co
+
1
5
F
sw
+ 55 KHz
The corner frequency of the output filter is calculated below;
F
LC
+
1
2 p 1 mH 3600 mF
Ǹ
+ 2.65 KHz
Check that the ESR zero frequency is not too high;
F
ESR
+
1
2 p R
ESR
C
O
t
F
co
10
F
ESR
+
1
2 p
45 mW
2
(1800 mF 2)
+ 2KHz
If ESR zero is larger than F
co
/10, Type III compensation
is necessary.
Choose C
C
for the crossover frequency and the soft start
C
C
+ 100 nF
The compensation capacitor (C
C
) is related to the loop
gain magnitude, zero position and the soft start. By adjusting
the value of this compensation capacitor, the crossover
frequency and the soft start time can be adjusted.
Zero of the compensation network is calculated as follows;
F
Z
+ F
LC
+ 2.65 KHz
R
C
+
1
2 p F
z
C
C
+
1
2 p 2.65 kHz 100 nF
+ 600.6 W
Pole of the compensation network is calculated as follows;
F
p
+ F
sw
+ 275 KHz
C
p
+
1
2 p F
p
R
C
+
1
2 p 275 kHz 600.6
+ 963.6 pF
The recommended compensation values are; R
C
= 604,
C
C
= 100 nF, C
P
= 1000 pF
