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IRLR8503PbF
Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that
period.
Table 3 – Control FET Losses
Table 4 – Synchronous FET Losses
Conduction
Loss
Gate Drive
Loss
Switching
Loss
Output
Loss
Losses associated with the Q
OSS
of the device every cycle when the control
FET turns on. Losses are caused by both FETs, but are dissipated by the control
FET.
Segment LossesDescription
Losses associated with MOSFET on time. I
RMS
is a function of load
current and duty cycle.
Losses associated with charging and discharging the gate of the
MOSFET every cycle. Use the control FET Q
G
.
Losses during the drain voltage and drain current transitions for every full cycle.
Losses occur during the Q
GS2
and Q
GD
time period and can be simplified by using
Q
switch
.
)on(DSRMSCOND
RIP ×=
2
ƒ××=
GGIN
QVP
ƒ××≈
ƒ×××≈
ƒ×××≈
G
SW
LINSWITCH
G
GD
LINQGD
G
GS
LINQGS
I
Q
IVP
I
Q
IVP
I
Q
IVP
2
2
FV
2
Q
P
IN
OSS
OUTPUT
××=
Conduction
Loss
Gate Drive
Loss
Switching
Loss
Output
Loss
Segment LossesDescription
Losses associated with MOSFET on time. I
RMS
is a function of load current and
duty cycle.
Losses associated with charging and discharging the gate of the MOSFET every
cycle. Use the Sync FET Q
G
.
Generally small enough to ignore except at light loads when the current reverses
in the output inductor. Under these conditions various light load power saving
techniques are employed by the control IC to maintain switching losses to a
negligible level.
Losses associated with the Q
OSS
of the device every cycle when the control FET
turns on. They are caused by the synchronous FET, but are dissipated in the control
FET.
DSonRMSCOND
RIP ×=
2
ƒ××=
GGIN
QVP
0P
SWITCH
≈
ƒ××=
IN
OSS
OUTPUT
V
Q
P
2
Figure 7. 2 & 3-FET solution for
Synchronous Buck Topology.
RLR8503
Control FET (Q1)
1 x IRLR8103 or
2 x IRLR8503
Synchronous
FET (Q2)
Typical PC Application
The IRLR8103V and the IRLR8503 are suitable for
Synchronous Buck DC-DC Converters, and are optimized
for use in next generation CPU applications. The
IRLR8103V is primarily optimized for use as the low side
synchronous FET (Q2) with low R
DS(on)
and high CdV/dt
immunity.The IRLR8503 is primarily optimized for use as
the high side control FET (Q2) with low cobmined Qsw and
R
DS(on)
, but can also be used as a synchronous FET. The
IRLR8503 is also tested for Cdv/dt immunity, critical for
the low side socket. The typical configuration in which
these devices may be used in shown in Figure 7.
V
or
