VEML7700
www.vishay.com
Vishay Semiconductors
Rev. 1.0, 19-Nov-15
4
Document Number: 84286
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION INFORMATION
VEML7700 is a cost effective solution of ambient light sensor with I
2
C bus interface. The standard serial digital interface is easy
to access “Ambient Light Signal” without complex calculation and programming by external controller.
1. Application Circuit
Fig. 6 - Application Diagram
Notes
• Proposed values for the pull-up resistor R1 and R2 should be > 1 kΩ, e.g. 2.2 kΩ to 4.7 kΩ.
For detailed description about set-up and use as well as more application related information see AN: “Designing VEML7700 into an
Application”.
2. I
2
C Interface
The VEML7700 contains actual six 16 bit command codes for operation control, parameter setup, and result buffering. All
registers are accessible via I
2
C communication. Figure 7 shows the basic I
2
C communication with VEML7700.
The built in I
2
C interface is compatible with I
2
C modes “standard” and “fast”: 10 kHz to 400 kHz.
I
2
C H-level range = 1.3 V to 3.6 V.
Please refer to the I
2
C specification from NXP for details.
Fig. 7 - Send Byte / Receive Byte Protocol
Register Addresses
VEML7700 has actual six user accessible 16 bit command
codes.
The addresses are 00h to 06h (03h not defined / reserved).
Device Address
The VEML7700 has a fix slave address for the host
programming and accessing selection.
The slave address (7 bit) is set to 0010000 = 0x10.
The least significant bit (LSB) defines read or write mode.
According 8 bit the bus address is then 0010 0000 = 20h for
write and 0010 0001 = 21h for read.
Auto-Memorization
VEML7700 can memorize the last ambient data before
shutdown and keep this data before waking up.
When VEML7700 is in shutdown mode, the host can freely
read this data via read command directly.
When VEML7700 wakes up, the data will be refreshed by
new detection.
Host
Micro Controller
I
2
C bus sata SDA
I
2
C bus clock SCL
VEML7700
SDA (4)
SCL (1)
GND (3)
V
DD
(2)
C2
C1
R3
100 nF10 μF
10R
2.5 V to 3.6 V
1.7 V to 3.6 V
R2
R1
C1 and R3
are optional
for very
disturbed
supply
Receive byte Read data from VEML7700
Send byte Write command to VEML7700
Host action
VEML7700 response
SSlave address A Command code AWr Data byte (LSB) A PData byte (MSB) A
SSlave address A Command code
A Data byte (LSB) A PData byte (MSB) N
Wr
SSlave address
Rd
A
S = start condition
P = stop condition
A = acknowledge
N = no acknowledge
