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Microsemi Corporation
Copyright 2012, Microsemi Corporation. All Rights Reserved.
ZL30343
SyncE/SONET/SDH G.8262/Stratum3 SETS
& IEEE 1588 Packet G.8261 Synchronizer
Short-Form Data Sheet
Features
• Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
• Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.813, and G.781
SETS
• Supports ITU-T G.823, G.824 and G.8261 for
2048 kbit/s and 1544 kbit/s interfaces
• Frequency, Phase and Time Synchronization over
IP, MPLS and Ethernet Packet Networks
• Frequency accuracy performance for WCDMA-
FDD, GSM, LTE-FDD and femtocell
applications, with target performance less than
± 15 ppb.
• Frequency performance for ITU-T G.823 and
G.824 synchronization interface, as well as
G.8261 PNT EEC, PNT PEC and CES interface
specifications.
• Phase Synchronization performance for
WCDMA-TDD, Mobile WiMAX, TD-SCDMA and
CDMA2000 applications with target
performance less than ± 1 s phase alignment.
• Time Synchronization for UTC-traceability and
GPS replacement.
• Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
• Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
• Programmable output synthesizers (P0, P1)
generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz
• Generates standard SONET/SDH clock rates
(e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz, 622.08 MHz) or Ethernet clock rates
(e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz,
312.5 MHz) for synchronizing Gigabit Ethernet
PHYs
• Provides two DPLLs which are independently
configurable through a serial interface
• Client reference switching between multiple
Servers
• Client holdover when Server packet connectivity is
lost
June 2012
Figure 1 - Functional Block Diagram
SONET/SDH/
Ethernet
APLL
dpll2_ref
diff0
diff1
apll_clk0
apll_clk1
apll_fp0
apll_fp1
Feedback
Synthesizer
fb_clk
ext_fb_clk
ext_fb_fp
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
Ref/Sync
Monitors
sync8
ref8
ref
n
/sync
n
ref
m
p0_clk0
p0_clk1
p0_fp0
p0_fp1
P1
Synthesizer
p1_clk0
p1_clk1
Input
Ports
DPLL2
T4
DPLL1
T0
P0
Synthesizer
I
2
C/SPI
JTAG
oscoosci
lockmode
hold
/N1
/N2
Software
PLL Control
(over I2C/SPI)
Ordering Information
ZL30343GGG 100 Pin CABGA Trays
ZL30343GGG2 100 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C