Philips Semiconductors Product data
74ALVCHS1683018-bit to 36-bit address driver with bus hold (3-State)
2002 Mar 15
8
From Output
Under Test
Load Circuit
Open
GND
TEST S
1
t
pd
t
PLZ
/t
PZL
Open
6 V
t
PHZ
/t
PZH
GND
SV01850
500 Ω
C
L
= 50 pF
(see Note A)
500 Ω
6 V
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V and 3.3 V ± 0.3 V
Timing
Input
1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V1.5 V
t
su
t
h
Voltage Waveforms
Setup and Hold Times
2.7 V
0 V
1.5 V1.5 V
t
w
Data
Input
Input
Voltage Waveforms
Pulse Duration
2.7 V
0 V
Input
1.5 V 1.5 V
t
PLH
V
OH
V
OL
1.5 V 1.5 V
t
PHL
Output
Voltage Waveforms
Propagation Delay Times
2.7 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
3 V
V
OL
V
OL
+ 0.3 V
t
PZL
t
PLZ
1.5 V
V
OH
0 V
V
OH
– 0.3 V
1.5 V
t
PZH
t
PHZ
Voltage Waveforms
Enable and Disable Times
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
S1
NOTES:
A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 2.5 ns, t
f
≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
Figure 2. Load circuit and voltage waveforms
