AD7804BRZ-REEL Datasheet AD7805CRZ, AD7809BSTZ, AD7808BRZ | P10-P12

AD7804/AD7805/AD7808/AD7809

REV. A–10–

DB15 (MSB) DB0 (LSB)

X MD0 = 1 MD1 = 0 A2* A1 A0 MX1 MX0 X X X STBY CLR 0 X X

X = Don’t Care

*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804 .

Figure 5. AD7804/AD7808 Channel Control Register Loading Sequence

DB15 (MSB) DB0 (LSB)

MAIN/SUB MD0 = X MD1 = 1 A2* A1 A0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X = Don’t Care

*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804 .

Figure 6. AD7804/AD7808 Main DAC Data Register Loading Sequence (

MAIN

/SUB = 0)

DB15 (MSB) DB0 (LSB)

MAIN/SUB MD0 = X MD1 = 1 A2* A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X

X = Don’t Care

*Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804.

Figure 7. AD7804/AD7808 Sub DAC Data Register Loading Sequence (

MAIN

/SUB = 1)

MSB LSB

X MD0 = 0MD1 = 0XXXXX0 BIN/COMP PD SSTBY SCLR 0 X X

X = Don’t Care

Figure 4. AD7804/AD7808 System Control Register Loading Sequence

AD7804/AD7808 SYSTEM CONTROL REGISTER (MD1 = 0,

MD0 = 0)

The bits in this register allow control over all DACs in the

package. The control bits include power down (PD), DAC input

coding select (BIN/COMP), system standby (SSTBY) and a

system clear (SCLR). The function of these bits is as follows:

Power Down (PD)

This bit in the control register is used to shut down the complete

device. With a 0 in this position, the reference and all DACs are

put into low power mode. Writing a 1 to this bit puts the part in

the normal operating mode. When in power-down mode, the

contents of all registers are retained and are valid when the

device is put back into normal operation.

Coding (BIN/COMP)

This bit in the system control register allows the user to select

one of two input coding schemes. The available schemes are

Twos complement coding and offset binary coding. All DACs

will be configured with the same input coding scheme. Writing

a zero to the control register selects twos complement coding,

while writing a 1 to this bit in the control register selects offset

binary coding.

With twos complement coding selected the output voltage from

the Main DAC is of the form :

OUT

BIAS

±V

SWING

where

SWING

×V

BIAS

With Offset Binary coding selected the output voltage from the

Main DAC ranges from:

OUT

BIAS

to V

OUT

BIAS

When the system control register is selected by writing zeros to

the mode bits, MD1 and MD0 the address bits are ignored as

the system control register controls all DACs in the package.

When MD1 = 0 and MD0 = 1, writing is to the channel control

fected by writing to this register. Each individual DAC has a

channel control register.

The DACs data registers are addressed by writing a one to

MD1 (DB13); the condition of MD0 (DB14) does not matter

when writing to the data registers. DB15 determines whether

writing is to the Main DAC data register or to the Sub DAC

data register. The Main DAC is 10 bits wide and the Sub DAC

is 8 bits wide. Thus when writing to the Sub DAC DB1 and

DB0 become don’t cares. The Sub DAC is used to offset the

complete transfer function of the Main DAC around its V

BIAS

point. The Sub DAC has 1/8 LSB resolution and will enable the

transfer function of the Main DAC to be offset by ± V

BIAS

/32.

When the LDAC line goes low, all DAC registers in the device

are simultaneously loaded with the contents of their respective

DAC data registers, and the outputs change accordingly.

Bringing the CLR line low resets the DAC data and DAC regis-

ters. This hardware clear affects both the Main and Sub DACs.

This operation sets the analog output of the Main DAC to V

BIAS

16 when offset binary coding is selected and the output is set to

BIAS

when twos complement coding is used. V

BIAS

is the output

of the internal multiplexer as shown in Figure 3. The output of

the Sub DAC is used to shift the transfer function of the Main

DAC around the V

BIAS

point and the contribution from the Sub

DAC is zero following an external hardware clear. Software

clears affect the Main DACs only.

AD7804/AD7805/AD7808/AD7809

–11–REV. A

BIAS

can be the internal bandgap reference, the internal V

reference or the external REFIN as determined by MX1 and

MX0 in the channel control register. A second external refer-

ence can be used if required by overdriving the V

/2 reference

which appears at the COMP pin.

System Standby (SSTBY)

This bit allows all the DACs in the package to be put into low

power mode simultaneously but the reference is not affected.

Writing a one to the SSTBY bit in the system control register

puts all DACs into standby mode. On writing a one to this bit

all linear circuitry is switched off and the DAC outputs are

connected through a high impedance to ground. The DACs come

out of standby mode when a 0 is written to the SSTBY bit.

System Clear Function (SCLR)

This function allows the user to clear the contents of all data

and DAC registers in software. Writing a one to the SCLR bit

in the control register clears the DAC’s outputs. A zero in this

bit position puts the DAC in normal operating mode. The out-

put of the Main DACs are cleared to one of two voltages de-

pending on the input coding used. If twos complement coding

is selected, then issuing a software clear will reset the output of

the Main DAC to midscale (V

BIAS

). If offset binary coding is

selected, the Main DAC output will be reset to V

BIAS

/16 follow-

ing the execution of a software clear. This system clear function

does not affect the Sub DAC; the Sub DAC data register retains

its value during a system software clear (SCLR).

AD7804/AD7808 CHANNEL CONTROL REGISTER (MD1 = 0,

MD0 = 1)

This register allows the user to have control over individual

DACs in the package. The control bits in this register include

the address bits for the selected DAC, standby (STBY), indi-

vidual DAC clear (CLR) and multiplexer output selection

(MX1 and MX0). The function of these bits follows.

DAC Selection (A2, A1, A0)

Bits A2, A1 and A0 in the input registers are used to address a

specific DAC. Table IIa shows the selection table for the DACs

of the AD7804. Table IIb shows the selection table for the

DACs of the AD7808.

Table IIa. DAC Selection Table for the AD7804

A2 A1 A0 Function

X 0 0 DAC A Selected

X 0 1 DAC B Selected

X 1 0 DAC C Selected

X 1 1 DAC D Selected

Table IIb. DAC Selection Table for the AD7808

A2 A1 A0 Function

0 0 0 DAC A Selected

0 0 1 DAC B Selected

0 1 0 DAC C Selected

0 1 1 DAC D Selected

1 0 0 DAC E Selected

1 0 1 DAC F Selected

1 1 0 DAC G Selected

1 1 1 DAC H Selected

Standby (STBY)

This bit allows the selected DAC in the package to be put into

low power mode. Writing a zero to the STBY bit in the channel

control register puts the selected DAC into standby mode. On

writing a zero to this bit all linear circuitry is switched off and

the DAC output is connected through a high impedance to

ground. The DAC is returned to normal operation by writing a

one to the STBY bit.

Software Clear Function (CLR)

This function allows the user to clear the contents of the se-

lected DAC’s data in software. Writing a one to the CLR bit in

the control register clears the DAC’s output. A zero in the CLR

bit position puts the DAC in normal operating mode. This

software CLR operation clears only the Main DAC, the con-

tents of the Sub DAC is unaffected by a CLR operation. The

output of the Main DAC can be cleared to one of two places

depending on the input coding used. An LDAC pulse is re-

quired to activate the channel clear function and must be ap-

plied after the bit in the channel control register is set or reset. If

twos complement coding is selected, then issuing a software

clear will reset the output of the Main DAC to midscale (V

BIAS

If offset binary coding is selected, the Main DAC output will be

reset to V

BIAS

/16 following the execution of a software clear.

Multiplexer Selection (MX1, MX0)

These two bits are used to select the reference input for the

selected DAC. Table III shows the options available.

Table III. Multiplexer Output Selection

MX1 MX0 V

BIAS

00V

0 1 INTERNAL V

REF

1 0 REFIN

1 1 Undetermined

AD7804/AD7808 SUB DAC DATA REGISTER

Figure 7 shows the loading sequence for writing to the data

registers of the DACs. DB15 determines whether writing is to

the Main or Sub DAC’s data register. A one in this position

selects the addressed Sub DAC’s data register. The Sub DAC is

8 bits wide and thus DB1 and DB0 of the 16-bit input word are

don’t cares when writing to the Sub DAC. This Sub DAC al-

lows the complete transfer function of each individual DAC to

be offset around the V

BIAS

point. This is achieved by either

adding or subtracting to the output of the Main DAC. This Sub

DAC has a span of

±V

BIAS

/32 with 1/8-bit resolution. The

coding scheme for the Sub DAC is the same as that for the

Main DAC. With offset binary coding the transfer function for

the Sub DAC is

BIAS

(NB – 128)

256

where NB is the digital code written to the Sub DAC and varies

from 0 to 255.

With twos complement coding the transfer function for the Sub

DAC is

BIAS

256

()

where NB is the digital code written to the Sub DAC and varies

from –128 to 127. V

BIAS

can be either the internal bandgap

reference, the internal V

/2 reference or the external REFIN as

AD7804/AD7805/AD7808/AD7809

REV. A–12–

determined by MX1 and MX0 in the channel control register as

shown in Table III. The internal V

/2 reference is provided at

the COMP pin. This internal reference can be overdriven with

an external reference thus providing the facility for two external

references.

AD7804/AD7808 POWER-UP CONDITIONS

When power is applied to the device, the device will come up in

standby mode where all the linear circuitry excluding the refer-

ence are switched off. Figure 8 shows the relevant default val-

ues for the system control register. Since a write to the system

control register is required to remove the standby condition the

only bits for which default conditions are applicable are PD and

SSTBY. Figure 9 details the relevant default conditions for the

Channel Control Register.

PD SSTBY

Figure 8. Default Conditions for System Control Register

on Power-Up

STBY CLR MX1 MX0

1 1 0 0

Figure 9. Default Conditions for Channel Control Register

on Power-Up

After power has been applied to the device the following proce-

dure should be followed to communicate and set up the device.

First, a write to the system control register is required to clear

the SSTBY bit and change the input coding scheme if required.

For example, to remove standby and set up offset binary input

coding 0060Hex should be written to the input register, if twos

complement coding is required 0020Hex should be written to

the input register. MD1 and MD0 are decoded in the input

control register.

Step two requires writing to the channel control register, which

allows individual control over each DAC in the package and

allows the V

BIAS

for the DAC to be selected as well as individual

DAC standby and clear functions. For example, if channel A is

to be configured for normal operation with internal reference

selected then 4110Hex should be written to the input register.

In the input register, the MD1 and MD0 bits are decoded in

association with the address bits to give access to the required

channel control register. The third and final step is to write data

to the selected DAC. To write half scale to channel A Main

DAC, 2200Hex should be written to the input register, the

MSB in the sixteen bit stream selects the Main DAC and the

next three bits address the DAC and the final 10 bits contain

the data. To write half scale to channel A Sub DAC, then A200

should be written to the input register. The flowchart in Figure

10 shows in graphic form the steps required in communicating

with the AD7804/AD7808.

WRITE TO SYSTEM

CONTROL REGISTER

WRITE TO CHANNEL

CONTROL REGISTER

SYSTEM

CONFIGURATION

CHANNEL

CONFIGURATION

DATA WRITE

ALL CHANNELS

CONFIGURED

DATA LOADING

COMPLETE

WRITE TO SELECTED

MAIN OR SUB DAC

DATA REGISTERS

CHANGE

CHANNEL

CONFIGURATION

CHANGE

SYSTEM

CONFIGURATION

END

POWER-UP

Figure 10. Flowchart for Controlling the DAC Following

Power-Up

AD7805/AD7809 INTERFACE SECTION

The AD7805 and AD7809 are parallel data input devices and

contain both control registers and data registers. The system

control register has global control over all DACs in the package

while the channel control register allows control over individual

DACs in the package. Two data registers are also available, one

for the 10-bit Main DAC and the second for the 8-bit Sub

DAC. In the parallel mode, CS and WR, in association with the

address pins, control the loading of data. Data is transferred

from the data register to the DAC register under the control of

the LDAC signal. Only data contained in the DAC register deter-

mines the analog output of any DAC. The timing diagram for

10-bit parallel loading is shown in Figure 2. The MODE pin on

the device determines whether writing is to the data registers or

to the control registers. When MODE is at a logic one, writing

is to the data registers. In the next write to the data registers a

bit in the channel control register determines whether the Main

DAC or the Sub DAC is addressed. This means that to address

either the Main or the Sub DAC the Main/Sub bit in the control

A logic zero on the mode pin enables writing to the control

control register or to the addressed channel control register.

Bringing the CLR line low resets the DAC registers to one of

two known conditions depending on the coding scheme se-

lected. The hardware clear affects both the Main and Sub

DAC registers. With offset binary coding a clear sets the output

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

AD7804BRZ-REEL

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Digital to Analog Converters - DAC 3.3V-5V Quad/ Octal 10-Bit

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AD7804BRZ-REEL

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