LTC6420CUDC-20#TRPBF Datasheet LTC6420CUDC-20#PBF, LTC6420IUDC-20#PBF, LTC6420CUDC-20#TRPBF | P10-P12

LTC6420-20

10

642020fb

APPLICATIONS INFORMATION

Figure 4a. Top Silkscreen of DC1299, Test Circuit A

Figure 4b. Demo Circuit 1299 Schematic (Test Circuit A)

642020 F04b

R7

OPT

R5

[2]

R9

[2]

C25

0.1µF

C22

0.1µF

C22

[1]

••

C21

[1]

C22

0.1µF

+INA

–INA

R11

OPT

R10

[2]

R12

[2]

C34

0.1µF

C31

[1]

C30

0.1µF

••

C30

0.1µF

C22

[1]

–INB

+INB

C18

0.1µF

C19

0.1µF

V

+

C18

0.1µF

C19

0.1µF

V

+

V

+

R1

1.21k

1%

R2

1k

1%

V

+

R16

1.21k

1%

R18

1k

1%

C16

0.1µF

TD4

V

OCMA

TD5

GND

TD3

GND

TD2

V

+

2.85V TO

3.5V

C35

1000pF

C32

1000pF

C30

0.1µF

C34

[1]

C17

[1]

C28

0.1µF

TD1

V

OCMB

R5

[1]

R3

1.5k

1%

V

+

V

+

R17

1.5k

1%

C43

0.1µF

1

2

3

5

4

12

T2

TCM4-19+

C39

0.1µF

+OUTA

–OUTA

C35

[1]

C40

0.1µF

C32

0.1µF

C41

[1]

R14

[1]

C44

0.1µF

1

2

3

5

4

12

T4

TCM4-19+

–OUTB

+OUTB

+INA

–INA

V

–

V

–

–INB

+INB

–OUTA

V

+

A

V

–

V

–

V

+

B

–OUTB

V

+

AV

OCMA

+OUTAENB

V

+

BV

–

V

OCMB

+OUTBENA

C42

0.1µF

C14

4.7µF

C15

1µF

V

+

VERSION

–C

–G

U1

LTC6420CUDC-20

LTC6421CUDC-20

R5, R9, R10, R13

NONE

T1, T3

TCM4-19+

NOTES: UNLESS OTHERWISE SPECIFIED

[1] DO NOT STUFF

[2]

R4

88.7

R5

88.7

R12

88.7

R15

88.7

ENA

JP1

DIS

EN

3

4

5

6

2

116

15

14

13

12

11

21 7 8 9 10

20 19 18 17

1

2

3

V

+

ENB

JP2

DIS

EN

1

2

3

J1

J2

J5

J7

J3

J4

J6

J8

1

2

3

5

4

1

2

3

5

4

12

[2]

T3

[2]

T1

U1

[2]

LTC6420-20

11

642020fb

TYPICAL APPLICATIONS

Test Circuit B, 4-Port Measurements

(Only the Signal-Path Connections Are Shown)

+

–

R5

49.9

3.3V 3.3V

R3

10

R4

10

R7

49.9

R8

49.9

V

OCM

C6

2.2µF

R6

49.9

1/2

LTC6420-20

1/2

LTC6420-20

C2

12pF

V

IN

C5

12pF

C3

12pF

642020 TA03

C1

0.1µF

C4

0.1µF

–3dB FILTER BANDWIDTH = 120MHz

LTC2208

V

CM

Parallel ADC Drivers to Reduce Wideband Noise

642020 TA02

–OUTA

+OUTA

+INA

0.1µF

PORT 1

(50Ω)

1/2

AGILENT

E5071C

PORT 2

(50Ω)

+

–

–INA

200Ω

R

OUT

12.5Ω

R

F

1000Ω

(B CHANNEL NOT SHOWN)

R

G

100Ω

R

F

1000Ω

R

OUT

12.5Ω

37.4Ω

R

G

100Ω

+

–

0.1µF

PORT 3

(50Ω)

1/2 AGILENT

E5071C

PORT 4

(50Ω)

LTC6420-20

12

642020fb

PACKAGE DESCRIPTION

UDC Package

20-Lead Plastic QFN (3mm × 4mm)

(Reference LTC DWG # 05-08-1742 Rev Ø)

3.00 ± 0.10

1.50 REF

4.00 ± 0.10

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

19 20

1

2

BOTTOM VIEW—EXPOSED PAD

2.50 REF

0.75 ± 0.05

R = 0.115

TYP

PIN 1 NOTCH

R = 0.20 OR 0.25

× 45° CHAMFER

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UDC20) QFN 1106 REV Ø

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

2.50 REF

3.10 ± 0.05

4.50 ± 0.05

1.50 REF

2.10 ± 0.05

3.50 ± 0.05

PACKAGE

OUTLINE

R = 0.05 TYP

1.65 ± 0.10

2.65 ± 0.10

1.65 ± 0.05

2.65 ± 0.05

0.50 BSC

LTC6420CUDC-20#TRPBF

LTC6420CUDC-20#TRPBF

Products related to this Datasheet