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TSH321
4/5
TEST WAVEFORM EVALUATION CIRCUIT
PRINTED CIRCUIT LAYOUT
As for any high frequency device, a few rules must
be observed when designing the PCB to get the
best performances from this high speed op amp.
From the most to the least important points :
❑ Each power supply lead has to be by-
passed to ground with a 10nF ceramic ca-
pacitor very close to the device and a 10µF
tantalum capacitor.
❑ To provide low inductance and low resist-
ance common return, use a ground plane
or common point return for power and sig-
nal.
❑ All leads must be wide and as short as pos-
sible especially for op amp inputs. This is in
order to decrease parasitic capacitance
and inductance.
❑ Use small resistor values to decrease time
constant with parasitic capacitance.
❑ Choose component sizes as small as pos-
sible (SMD).
❑ On output, decrease capacitor load so as
to avoid circuit stability being degraded
which may cause oscillation. You can also
add a serial resistor in order to minimise its
influence.
❑ One can add in parallel with feedback re-
sistor a few pF ceramic capacitor C
F
adjust-
ed to optimize the settling time.
V
in
50%
t
d
t
r
90%
t
s
0.1% of edge amplitude
10%
Input
50
Ω
1kΩ
1kΩ
10nF
10µF
C
F
-5V
+5V
10nF
10
µ
F
50
Ω
Output
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