Errata ID Errata Title
7027 UART: During ISO-7816 T=0 initial character detection invalid initial characters are stored in the RxFIFO
7028 UART: During ISO-7816 initial character detection the parity, framing, and noise error flags can set
6472 UART: ETU compensation needed for ISO-7816 wait time (WT) and block wait time (BWT)
4647 UART: Flow control timing issue can result in loss of characters if FIFO is not enabled
7029 UART: In ISO-7816 T=1 mode, CWT interrupts assert at both character and block boundaries
7090 UART: In ISO-7816 mode, timer interrupts flags do not clear
7031 UART: In single wire receive mode UART will attempt to transmit if data is written to UART_D
5704 UART: TC bit in UARTx_S1 register is set before the last character is sent out in ISO7816 T=0 mode
7091 UART: UART_S1[NF] and UART_S1[PE] can set erroneously while UART_S1[FE] is set
7092 UART: UART_S1[TC] is not cleared by queuing a preamble or break character
5928 USBOTG: USBx_USBTRC0[USBRESET] bit does not operate as expected in all cases
6933 eDMA: Possible misbehavior of a preempted channel when using continuous link mode
e6804: CJTAG: Performing a mode change from Standard Protocol to Advanced
Protocol may reset the CJTAG.
Errata type: Errata
Description: In extremely rare conditions, when performing a mode change from Standard Protocol to
Advanced Protocol on trhe IEEE 1149.7 (Compact JTAG interface) , the CJTAG may reset
itself. In this case, all internal CJTAG registers will be reset and the CJTAG will return to the
Standard Protocol mode.
Workaround: If the CJTAG resets itself while attempting to change modes from Standard Protocol to
Advanced Protocol and Advanced Protocol cannot be enabled after several attempts, perform
future accesses in Standard Protocol mode and do not use the Advanced Protocol feature.
e6939: Core: Interrupted loads to SP can cause erroneous behavior
Errata type: Errata
Description: ARM Errata 752770: Interrupted loads to SP can cause erroneous behavior
Affects: Cortex-M4, Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
Description
If an interrupt occurs during the data-phase of a single word load to the stack-pointer (SP/
R13), erroneous behavior can occur. In all cases, returning from the interrupt will result in the
load instruction being executed an additional time. For all instructions performing an update to
the base register, the base register will be erroneously updated on each execution, resulting in
the stack-pointer being loaded from an incorrect memory location.
The affected instructions that can result in the load transaction being repeated are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
2 Freescale Semiconductor, Inc.
