85210AY-31 www.idt.com REV. C JULY 10, 2012
1
ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85210-31 is a low skew, high performance
dual 1-to-5 Differential-to-HSTL Fanout Buffer.The
CLKx, nCLKx pairs can accept most standard differential
input levels. The ICS85210-31 is characterized to
operate from a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make
the ICS85210-31 ideal for those clock distribution
applications demanding well defined performance
and repeatability.
FEATURES
Dual 1-to-5 HSTL compatible bank outputs
2 selectable differential clock input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
Maximum output frequency: 650MHz
Translates any single ended input signal to
LVHSTL levels with resistor bias on nCLKx inputs
Output skew: 50ps (maximum)
Part-to-part skew: 350ps (maximum)
Propagation delay: 2ns (maximum)
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
V
DD
CLK0_EN
CLK0
nCLK0
CLK1_EN
CLK1
nCLK1
GND
VDDO
QB2
nQB2
QB3
nQB3
QB4
nQB4
V
DDO
VDDO
nQA2
QA2
nQA1
QA1
nQA0
QA0
V
DDO
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS85210-31
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
CLK0
nCLK0
CLK0_EN
D
Q
LE
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
CLK1
nCLK1
CLK1_EN
D
Q
LE
85210AY-31 www.idt.com REV. C JULY 10, 2012
2
ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
rebmuNemaNepyTnoitpircseD
1V
DD
rewoP.nipylppuseroC
2NE_0KLCpulluPpulluP.elbanekcolcgnizinorhcnyS
30KLCtupnInwodlluP.tupnikcolclaitnereffidgnitr
evni-noN
40KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
5NE_1KLCpulluPpulluP.elbanekcolcgnizinorhcnyS
61KLCtupn
InwodlluP.tupnikcolclaitnereffidgnitrevni-noN
71KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
8DNGrewoP.dnuorg
ylppusrewoP
,61,9
23,52
V
ODD
rewoP.snipylppustuptuO
11,014BQ,4BQntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
31,213BQ,3BQntuptuO.slev
elecafretniLTSH.riaptuptuolaitnereffiD
51,412BQ,2BQntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
81,7
11BQ,1BQntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
02,910BQ,0BQntuptuO.slevelecafretniLTSH.riaptuptu
olaitnereffiD
22,124AQ,4AQntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
42,323AQ,3AQntuptuO.slevelecafre
tniLTSH.riaptuptuolaitnereffiD
72,622AQ,2AQntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
92,821AQ,1AQnt
uptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
13,030AQ,0AQntuptuO.slevelecafretniLTSH.riaptuptuolaitner
effiD
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
85210AY-31 www.idt.com REV. C JULY 10, 2012
3
ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
NE_1KLC,NE_0KLC4BQ:0BQ,4AQ:0AQ4BQn:0BQn,4AQ:0AQn
0WOL;delbasiDHGIH;delbasiD
1delbanEdelbanE
egdekc
olctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
.1erugiFninwohssa
stupni1KLCn,1KLCdna0KLCn,0KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
.B3elbaTnidebircsedsa
stupnIstuptuO
edoMtuptuOottupnIytiraloP
1KLCro0KLC1KLCnro0KLCn
,4AQ:0AQ
4BQ:0BQ
,4AQn:0AQn
4BQn:0BQn
00 WOLHGIHlaitn
ereffiDotlaitnereffiDgnitrevnInoN
11 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffi
DotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnere
ffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
."sleveLdednEelgniStpeccAot
tupnIlaitnereffiDehtgniriW",noitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
FIGURE 1. CLK_EN TIMING DIAGRAM
Enabled
Disabled
nCLK0, nCLK1
CLK0, CLK1
CLK0_EN,
CLK1_EN
nQA0:nQA4,
nQB0:nQB4
QA0:QA4,
QB0:QB4

85210AY-31LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution DUAL 5 OUT HSTL BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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