CY7C1399BNL-12ZXC Datasheet CY7C1399BN-12VXIT, CY7C1399BN-12ZXCT, CY7C1399BN-12VXI | P4-P6

CY7C1399BN

Document Number: 001-06490 Rev. *H Page 4 of 16

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Storage temperature ................................ –65 C to +150 C

Ambient temperature with

power applied .......................................... –55 C to +125 C

Supply voltage on

to relative GND

[1]

................................–0.5 V to +4.6 V

DC voltage applied to outputs

in high Z State

[1]

.................................–0.5 V to V

+ 0.5 V

DC input voltage

[1]

............................. –0.5 V to V

+ 0.5 V

Output current into outputs (LOW) ............................. 20 mA

Static discharge voltage

(per MIL-STD-883, Method 3015) .......................... >2001 V

Latch-up current .................................................... >200 mA

Operating Range

Range Ambient Temperature V

Commercial 0C to +70C 3.3 V 300 mV

Industrial –40

C to +85C

Automotive-A –40

C to +85C

Electrical Characteristics

Over the Operating Range

Parameter

[1]

Description Test Conditions

-12 -15

Unit

Min Max Min Max

Output HIGH voltage Min V

, I

= –2.0 mA 2.4 – 2.4 – V

Output LOW voltage Min V

, I

= 4.0 mA – 0.4 – 0.4 V

Input HIGH voltage 2.2 V

+ 0.3 2.2 V

+ 0.3 V

[1]

Input LOW voltage –0.3 0.8 –0.3 0.8 V

Input leakage current –1 +1 –1 +1 A

Output leakage current GND  V

 V

, Output disabled –5 +5 –5 +5 A

operating supply current Max V

, I

OUT

= 0 mA,

f = f

MAX

= 1/t

–55–50mA

SB1

Automatic CE power-down

current – TTL inputs

Max V

, CE  V

 V

, or

 V

f = f

MAX

Commercial–5––mA

Commercial (L)–4––mA

Industrial –5–5mA

Automotive-A–––5mA

SB2

Automatic CE Power-down

current – CMOS inputs

[2]

Max V

 V

– 0.3 V,

 V

– 0.3 V, or

 0.3 V,

WE V

– 0.3 V or

WE 0.3 V,

f=f

MAX

Commercial – 500 – – A

Commercial (L) – 50 – – A

Industrial – 500 – 500 A

Automotive-A – – – 500 A

Notes

1. Minimum voltage is equal to –2.0 V for pulse durations of less than 20 ns.

2. Device draws low standby current regardless of switching on the addresses.

CY7C1399BN

Document Number: 001-06490 Rev. *H Page 5 of 16

Capacitance

Parameter

[3]

Description Test Conditions Max Unit

: Addresses Input capacitance T

= 25C, f = 1 MHz, V

= 3.3 V 5 pF

: Controls 6pF

OUT

Output capacitance 6pF

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms

[4]

3.0 V

3.3 V

OUTPUT

R1 317



351

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

 3ns

 3

OUTPUT 1.73 V

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

167

Data Retention Characteristics

(Over the Operating Range - L version only)

Parameter Description Conditions Min Max Unit

for data retention 2.0 – V

CCDR

Data retention current V

= V

= 2.0 V,

> V

– 0.3 V,

> V

– 0.3 V or V

< 0.3 V

020A

CDR

Chip deselect to data retention

time

0–ns

Operation recovery time t

–ns

Data Retention Waveform

Figure 4. Data Retention Waveform

3.0 V3.0 V

CDR

 2 V

DATA RETENTION MODE

Notes

3. Tested initially and after any design or process changes that may affect these parameters.

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I

and capacitance C

= 30 pF.

CY7C1399BN

Document Number: 001-06490 Rev. *H Page 6 of 16

Switching Characteristics

Over the Operating Range

Parameter

[5]

Description

-12 -15

Unit

Min Max Min Max

Read Cycle

Read cycle time 12 – 15 – ns

Address to data valid – 12 – 15 ns

OHA

Data hold from address change 3 – 3–ns

ACE

CE LOW to data valid – 12 – 15 ns

DOE

OE LOW to data valid – 5 – 6 ns

LZOE

OE LOW to low Z

[6]

0–0–ns

HZOE

OE HIGH to high Z

[6, 7]

–5–6 ns

LZCE

CE LOW to low Z

[6]

3–3–ns

HZCE

CE HIGH to high Z

[6, 7]

–6–7 ns

CE LOW to power-up 0 – 0–ns

CE HIGH to power-down – 12 – 15 ns

Write Cycle

[8, 9]

Write cycle time 12 – 15 – ns

SCE

CE LOW to write end 8 – 10 – ns

Address setup to write end 8 – 10 – ns

Address hold from write end 0 – 0–ns

Address setup to write start 0 – 0–ns

PWE

WE pulse width 8 – 10 – ns

Data setup to write end 7 – 8–ns

Data hold from write end 0 – 0–ns

HZWE

WE low to high Z

[8]

–7–7 ns

LZWE

WE high to low Z

[6]

3–3–ns

Notes

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I

and capacitance C

= 30 pF.

6. At any given temperature and voltage condition, t

HZCE

is less than t

LZCE

, t

HZOE

is less than t

LZOE

, and t

HZWE

is less than t

LZWE

for any given device.

7. t

HZOE

, t

HZCE

, t

HZWE

are specified with C

= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.

8. The internal write time of the memory is defined by the overlap of CE

LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

9. The minimum write cycle time for Write Cycle No. 3 (WE

Controlled, OE LOW) is the sum of t

HZWE

and t

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

CY7C1399BNL-12ZXC

Mfr. #:

Buy CY7C1399BNL-12ZXC

Manufacturer:

Cypress Semiconductor

Description:

SRAM 256Kb 3.3V 12ns 32K x 8 SRAM

Lifecycle:

New from this manufacturer.

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CY7C1399BNL-12ZXC

CY7C1399BNL-12ZXC

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