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MAX1167CCEE+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
signal to restart the external clock (SCLK). To read the
entire conversion result, 16 SCLK cycles are needed.
Extra clock pulses, occurring after the conversion result
has been clocked out and prior to the rising edge of
CS, cause the conversion result to be shifted out again.
The MAX1167/MAX1168 internal clock 8-bit-wide data-
transfer mode requires 24 external clock cycles and 25
internal clock cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
CSW
). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1167/MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1167/MAX1168 in the internal clock mode. Enable
scanning by setting bits 4 and 3 in the command/con-
figuration/control register (see Tables 3 and 4). In scan
mode, conversion results are stored in memory until the
completion of the last conversion in the sequence.
Upon completion of the last conversion in the
sequence, EOC transitions from high to low to indicate
the end of the conversion and shuts down the internal
oscillator. Use the EOC high-to-low transition as the sig-
nal to restart the external clock (SCLK). DOUT provides
the conversion results in the same order as the channel
conversion process. The MSB of the first conversion is
available at DOUT on the falling edge of EOC (Figure 14).
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 19
DOUT
CS
SCLK
DIN
EOC
X X X X X X X X
DATA
LSB
X
t
ACQ
CONFIGURATION
X = DON
,
T CARE
DSPR = DSEL = DV
DD
t
CONV
POWER-DOWN
ADC
STATE
INTERNAL
CLK
1
89 16
21332
2417 32
MSB
Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
DOUT
CS
SCLK
DIN
EOC
ADC
STATE
INTERNAL
CLK
1
8
940
2
6
24
48
3026
1
MSB
LSB
LSB
X
MSB
t
ACQ
CONFIGURATION
POWER-DOWN
t
CONV
t
ACQ
t
CONV
X = DON
,
T CARE
DSPR = DV
DD
, DSEL = GND (MAX1168 ONLY)
Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing
MAX1167/MAX1168
Internal Clock 16-Bit-Wide Data-Transfer and Scan
Mode (MAX1168 Only)
Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the
rising edge of SCLK. The command/configuration/con-
trol register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1168 selects the proper channel for
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external clock
while the internal clock is on. Turning off SCLK ensures
lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the inter-
nal clock and ends on the falling edge of the 18th inter-
nal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuitry
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
20 ______________________________________________________________________________________
DOUT
CS
SCLK
DIN
EOC
ADC
STATE
INTERNAL
CLK
1
89 16
X = DON
,
T CARE
2
13
17
45
48
64
32 34
X X X X X X X X
DATA
LSB
X
t
ACQ
POWER-DOWNt
CONV
t
ACQ
t
CONV
MSB
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only)
CS
SCLK
DSPR
DIN
DOUT
t
CSS
t
CL
t
DS
t
DH
t
DV
t
CH
t
DO
t
TR
t
FSH
t
CSH
t
DF
t
CP
t
CSW
t
FSS
...
...
...
...
...
Figure 16. Detailed DSP-Interface Timing (MAX1168 Only)
are shut down on the EOC high-to-low transition. Use
the EOC high-to-low transition as the signal to restart
the external clock (SCLK). To read the entire conver-
sion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
the conversion result to be shifted out again. The
MAX1168 internal-clock 16-bit-wide data-transfer mode
requires 32 external clock cycles and 32 internal clock
cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
CSW
). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1168 in internal clock mode. Enable scanning by
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 21
DOUT
CS
DSPR
SCLK
DIN
DSPX
0
MSB
LSB
MSB LSB
t
ACQ
IDLE
t
CONV
ADC
STATE
1
8
16
24
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
DOUT
CS
SCLK
DIN
0
MSB
LSB
MSB
LSB
ADC
STATE
16 24 32
1
8
XXXXX
X
XX
X = DON
,
T CARE
t
ACQ
IDLE
t
CONV
DSPR
DSPX
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

MAX1167CCEE+

Mfr. #:
Buy MAX1167CCEE+
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Integrated Circuits (ICs) Analog to Digital Converters - IC ADC 16BIT 200KSPS 16-QSOP
Lifecycle:
New from this manufacturer.
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