NOT RECOMMENDED FOR NEW DESIGNS DS1225Y
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
at V
before Power-Down
PD
CC
TP
F
µ
CC
TP
R
µ
at V
IH
after Power-Up
REC
(T
A
= +25°C)
Expected Data Retention Time
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
is high for a read cycle.
2.
= V
IH
or V
IL
. If
= V
IH
during a write cycle, the output buffers remain in a high impedance
state.
3. t
WP
is specified as the logical AND of
and
. t
WP
is measured from the latter of
or
going low to the earlier of
or
going high.
4. t
DS
is measured from the earlier of
or
going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
low transition occurs simultaneously with or later than the
low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.
7. If the
high transition occurs prior to or simultaneously with the
high transition, the output
buffers remain in a high-impedance state during this period.
