The MAX7301 is written to using the following
sequence:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN—D15 first, D0 last—
observing the setup and hold times (bit D15 is low,
indicating a write command).
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low).
5) Take SCLK low (if not already low).
Figure 4 shows a write operation when 16 bits are
transmitted.
It is acceptable to clock more than 16 bits into the
MAX7301 between taking CS low and taking CS high
again. In this case, only the last 16 bits clocked into the
MAX7301 are retained.
Reading Device Registers
Any register data within the MAX7301 may be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low (this enables the internal 16-bit Shift
register).
3) Clock 16 bits of data into DIN—D15 first to D0 last.
D15 is high, indicating a read command and bits
D14 through D8 containing the address of the regis-
ter to be read. Bits D7–D0 contain dummy data,
which is discarded.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low), positions D7 through D0 in the Shift register
are now loaded with the register data addressed by
bits D1 through D8.
5) Take SCLK low (if not already low).
6) Issue another read or write command (which can
be a No-Op), and examine the bit stream at DOUT;
the second 8 bits are the contents of the register
addressed by bits D1 through D8 in step 3.
MAX7301
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
_______________________________________________________________________________________ 7
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
R/W
8
CEDATA
8
PORT REGISTERS
GPIO
CONFIGURATION
P4 TO P31
GPIO DATA
R/W
CONFIGURATION
REGISTERS
PORT CHANGE
DETECTOR
MASK REGISTER
COMMAND
REGISTER DECODE
8
DATA BYTE COMMAND BYTE
CS
DIN
SCLK
DOUT
8
Figure 1. MAX7301 Functional Diagram
MAX7301
Initial Power-Up
On initial power-up, all control registers are reset, and
the MAX7301 enters shutdown mode (Table 4).
Transition (Port Data Change) Detection
Port transition detection allows any combination of the
seven ports P24–P30 to be continuously monitored for
changes in their logic status (Figure 5). A detected
change is flagged on port P31, which is used as an
active-high interrupt output (INT). Note that the
MAX7301 does not identify which specific port(s)
caused the interrupt, but provides an alert that one or
more port levels have changed.
The mask register contains 7 mask bits that select
which of the seven ports, P24–P30 are to be monitored
(Table 8). Set the appropriate mask bit to enable that
port for transition detect. Clear the mask bit if transitions
on that port are to be ignored. Transition detection
works regardless of whether the port being monitored is
set to input or output, but generally it is not particularly
useful to enable transition detection for outputs.
Port P31 must be configured as an output in order to
work as the interrupt output INT when transition detec-
tion is used. Port P31 is set as output by writing bit D7
= 0 and bit D6 = 1 to the port configuration register
(Table 1).
To use transition detection, first set up the mask regis-
ter and configure port P31 as an output, as described
above. Then enable transition detection by setting the
M bit in the configuration register (Table 7). Whenever
the configuration register is written with the M bit set,
the MAX7301 updates an internal 7-bit snapshot regis-
ter, which holds the comparison copy of the logic states
of ports P24 through P30. The update action occurs
regardless of the previous state of the M bit, so that it is
not necessary to clear the M bit and then set it again to
update the snapshot register.
When the configuration register is written with the M bit
set, transition detection is enabled and remains
enabled until either the configuration register is written
with the M bit clear, or a transition is detected. The INT
output port P31 goes low, if it was not already low.
Once transition detection is enabled, the MAX7301
continuously compares the snapshot register against
the changing states of P24 through P31. If a change on
any of the monitored ports is detected, even for a short
time (like a pulse), INT output port P31 is latched high.
The INT output is not cleared if more changes occur or
if the data pattern returns to its original snapshot condi-
tion. The only way to clear INT is to access (read or
write) the transition detection mask register (Table 8).
Transition detection is a one-shot event. When INT has
been cleared after responding to a transition event,
transition detection is automatically disabled, even
though the M bit in the configuration register remains
set (unless cleared by the user). Reenable transition
detection by writing the configuration register with the
M bit set, to take a new snapshot of the seven ports
P24 to P30.
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
8 _______________________________________________________________________________________
t
CSH
t
CL
t
CSS
t
CH
t
CSH
CS
SCLK
DIN
DOUT
t
DS
t
DH
t
DO
Figure 2. 4-Wire Interface
External Component R
ISET
The MAX7301 uses an external resistor, R
ISET
, to set
internal biasing. Use a resistor value of 39k.
Applications Information
Low-Voltage Operation
The MAX7301 operates down to 2V supply voltage
(although the sourcing and sinking currents are not
guaranteed), providing that the MAX7301 is powered
up initially to at least 2.5V to trigger the device’s internal
reset, and also that the serial interface is constrained to
10Mbps.
SPI Routing Considerations
The MAX7301’s SPI interface is guaranteed to operate
at 26Mbps on a 2.5V supply, and on a 5V supply typi-
cally operates at 50Mbps. This means that transmission
line issues should be considered when the interface
connections are longer than 100mm, particularly with
higher supply voltages. Ringing manifests itself as
communication issues, often intermittent, typically due
to double clocking due to ringing at the SCLK input. Fit
a 1k to 10k parallel termination resistor to either
GND or V+ at the DIN, SCLK, and CS input to damp
ringing for moderately long interface runs. Use line-
impedance matching terminations when making con-
nections between boards.
PC Board Layout Considerations
For the TQFN version, connect the underside exposed
pad to GND. Ensure that all the MAX7301 GND connec-
tions are used. A ground plane is not necessary, but
may be useful to reduce supply impedance if the
MAX7301 outputs are to be heavily loaded. Keep the
track length from the ISET pin to the R
ISET
resistor as
short as possible, and take the GND end of the resistor
either to the ground plane or directly to the ground pins.
Power-Supply Considerations
The MAX7301 operates with power-supply voltages of
2.5V to 5.5V. Bypass the power supply to GND with a
0.047µF capacitor as close to the device as possible.
Add a 1µF capacitor if the MAX7301 is far away from
the board’s input bulk decoupling capacitor.
Chip Information
TRANSISTOR COUNT: 30,316
PROCESS: CMOS
MAX7301
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
_______________________________________________________________________________________ 9
MICROCONTROLLER
SERIAL-DATA OUTPUT
SERIAL CS OUTPUT
SERIA-CLOCK OUTPUT
SERIAL-DATA INPUT
DIN
SCLK
CS
DOUT
DIN
SCLK
CS
DOUT
DIN
SCLK
CS
DOUT
MAX7301
MAX7301
MAX7301
Figure 3. Daisy-Chain Arrangement for Controlling Multiple MAX7301s
.
D15
= 0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 = 0
CS
SCLK
DIN
DOUT
Figure 4. Transmission of a16-Bit Write to the MAX7301

MAX7301ATL+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Interface - I/O Expanders 2.5-5.5V 20/28 Port I/O Expander
Lifecycle:
New from this manufacturer.
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