MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Detailed Description
The MAX9248/MAX9250 DC-balanced deserializers
operate at a 2.5MHz-to-42MHz parallel clock frequen-
cy, deserializing video data to the RGB_OUT[17:0] out-
puts when the data-enable output DE_OUT is high, or
control data to the CNTL_OUT[8:0] outputs when
DE_OUT is low. The outputs on the MAX9248 are pro-
grammable for ±2% or ±4% spread relative to the
LVDS input clock frequency, while the MAX9250 has no
spread, but has an output-enable input that allows out-
put busing. The video phase words are decoded using
two overhead bits, EN0 and EN1. Control phase words
are decoded with one overhead bit, EN0. Encoding,
performed by the MAX9247 serializer, reduces EMI and
maintains DC balance across the serial cable. The seri-
al-input word formats are shown in Tables 1 and 2.
Control data inputs C0 to C4, each repeated over three
serial bit times by the serializer, are decoded using
majority voting. Two or three bits at the same state
determine the state of the recovered bit, providing sin-
gle bit-error tolerance for C0 to C4. The state of C5 to
C8 is determined by the level of the bit itself (no voting
is used).
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two
capacitors are sufficient for isolation, but four capaci-
tors—two at the serializer output and two at the deseri-
alizer input—provide protection if either end of the
cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
The MAX9247 serializer can also be DC-coupled to the
MAX9248/MAX9250 deserializers. Figures 12 and 14
show the AC-coupled serializer and deserializer with
two capacitors per link, and Figures 13 and 15 show
the AC-coupled serializer and deserializer with four
capacitors per link.
Applications Information
Selection of AC-Coupling Capacitors
See Figure 16 for calculating the capacitor values for
AC-coupling depending on the parallel clock frequen-
cy. The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
Termination and Input Bias
The IN+ and IN- LVDS inputs are internally connected
to +1.2V through 42kΩ (min) to provide biasing for AC-
coupling (Figure 1). Assuming 100Ω interconnect, the
LVDS input can be terminated with a 100Ω resistor.
Match the termination to the differential impedance of
the interconnect.
Use a Thevenin termination, providing 1.2V bias, on an
AC-coupled link in noisy environments. For intercon-
nect with 100Ω differential impedance, pull each LVDS
line up to V
CC
with 130Ω and down to ground with 82Ω
at the deserializer input (Figures 12 and 15). This termi-
nation provides both differential and common-mode
termination. The impedance of the Thevenin termination
should be half the differential impedance of the inter-
connect and provide a bias voltage of 1.2V.
