7
FIGURE 3A. MEASUREMENT POINTS
C
L
includes fixture and stray capacitance.
Reconfigure accordingly to test SW3 and SW4.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL8393 ONLY)
Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
Repeat test for all switches.
FIGURE 5. R
ON
TEST CIRCUIT
Test Circuits and Waveforms (Continued)
90%
3V
0V
t
D
0V
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
90%
t
D
0V
V
OUT1
V
OUT2
90%
90%
LOGIC
INPUT
IN1
COM1
R
L1
C
L1
V
OUT1
300
35pF
COM2
R
L2
C
L2
V
OUT2
300
35pF
NO1
NC2
GND
IN2
V
NX
V+
C
C
V-
C
ANALYZER
R
L
SIGNAL
GENERATOR
V+
C
0V OR 2.4V
NO OR NC
COM
IN
GND
C
V-
V+
C
0.8V OR 2.4V
NO OR NC
COM
IN
GND
V
NX
V
1
R
ON
= V
1
/1mA
1mA
C
V-
ISL8391, ISL8392, ISL8393
8
Detailed Description
The ISL8391–ISL8393 quad analog switches offer precise
switching capability from a bipolar ±2V to ±6V or a single 2V
to 12V supply with low on-resistance (20) and high speed
switching (t
ON
= 60ns, t
OFF
= 30ns). The devices are
especially well suited to portable battery powered equipment
thanks to the low operating supply voltage (2V), low power
consumption (1µW), low leakage currents (2.5nA max). High
frequency applications also benefit from the wide bandwidth,
and the very high OFF isolation and crosstalk rejection.
Supply Sequencing And Overvoltage Protection
As with any CMOS device, proper power supply sequencing
is required to protect the device from excessive input
currents which might permanently damage the IC. All I/O
pins contain ESD protection diodes from the pin to V+ and to
V- (see Figure 8). To prevent forward biasing these diodes,
V+ and V- must be applied before any input signals, and
input signal voltages must remain between V+ and V-. If
these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
Adding a series resistor to the switch input defeats the
purpose of using a low R
ON
switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
Power-Supply Considerations
The ISL839X construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL839X 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (
±6V or 12V single supply),
as well as room for overshoot and noise spikes.
This family of switches performs equally well when operated
with bipolar or single voltage supplies, and bipolar supplies
need not be symmetrical. The minimum recommended
supply voltage is 2V or
±2V. It is important to note that the
input signal range, switching times, and ON-resistance
degrade at lower supply voltages. Refer to the electrical
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
0V OR 2.4V
ANALYZER
V+
C
NO1 OR NC1
SIGNAL
GENERATOR
R
L
GND
IN1
COM1
IN2
50
0V OR 2.4V
NO
COM2
NO2 OR NC2
C
V-
CONNECTION
V+
GND
NO OR NC
COM
IN
IMPEDANCE
ANALYZER
0V OR 2.4V
V-
FIGURE 8. OVERVOLTAGE PROTECTION
V-
V
COM
V
NO OR NC
OPTIONAL PROTECTION
V+
IN
X
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
ISL8391, ISL8392, ISL8393
9
specification tables and Typical Performance Curves for
details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals, so switch parameters -
especially R
ON
- are strong functions of both supplies.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.5V
to 10V. At 12V the V
IH
level is about 2.7V, so for best results
use a logic family that provides a V
OH
greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
200MHz (see Figure 15), with a small signal -3dB bandwidth
in excess of 300MHz, and a large signal bandwidth
exceeding 300MHz.
An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. OFF Isolation
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 16 details the high OFF Isolation and
Crosstalk rejection provided by this family. At 10MHz, OFF
isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease OFF Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
Typical Performance Curves T
A
= 25
o
C, Unless Otherwise Specified
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
R
ON
()
V+ (V)
V
COM
= (V+) - 1V
I
COM
= 1mA
4681012
0
12.5
25
37.5
50
62.5
357911
V- = -5V
-40
o
C
85
o
C
V- = 0V
25
o
C
10
15
20
25
25
o
C
-40
o
C
85
o
C
15
20
25
30
35
20
30
40
50
60
30
40
50
60
70
80
R
ON
()
V
COM
(V)
024135
V+ = 2.7V
V+ = 5V
25
o
C
-40
o
C
85
o
C
I
COM
= 1mA
V- = 0V
V- = 0V
V+ = 3.3V
25
o
C
-40
o
C
85
o
C
V- = 0V
25
o
C
85
o
C
-40
o
C
20
ISL8391, ISL8392, ISL8393

ISL8391IB

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC SWITCH QUAD SPST 16SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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