10
FN9191.2
December 5, 2008
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is selected. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a predetermined interval. When in static mode, the OLF bit
goes HIGH when the current clamp limit is reached and
returns LOW when the overload condition is cleared. The
OLF/BCF bit will be LOW at the end of initial power-on soft-
start. In the static mode the output current through the linears
is limited to a 990mA typical.
When a 19.3V line is connected onto a VOUT1 or 2 that has
been set to 13.3V the linear will then enter a back current
limited state. When a back current of greater than 125mA
typical is sensed at the lower FET of the linear for a period
greater that 100µs, the output is disabled for a period of 5ms
and the BCF bit is set. If the 19.3V remains connected, the
output will cycle through the ON = 100µs/OFF = 5ms. The
output will recover when the fault is removed.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. When the junction is cooled down to +130°C
(typical), normal operation is resumed and the OTF bit is
reset LOW.
In over temperature conditions, the OTF flag goes HIGH and
the I
2
C data will be cleared. The user may need to monitor
the I
2
C enable bits and OTF flag continuously and enable
the chip, if I
2
C data is cleared. OTF conditions may also
make the OLF flags go HIGH, when high capacitive loads
are present or self-heating conditions occur at higher loads.
External Output Voltage Selection
When the I
2
C bit VSPEN is set high the output voltage can
be selected by the I
2
C bus. Additionally, the package offers
the pin SELVTOP for independent 13V thru 19V output
voltage selection, when the VSPEN bit is set low. A
summary of the voltage control is given in the Table 1. For
further details refer to the individual registers SR1 and SR3
I
2
C Bus Interface for ISL6423
(Refer to Philips I
2
C Specification, Rev. 2.1)
Data transmission from main microprocessor to the ISL6423
and vice versa takes place through the two wire I
2
C bus
interface, consisting of the two lines SDA and SCL. Both
SDA and SCL are bidirectional lines, connected to a positive
supply voltage via a pull up resistor. (Pull-up resistors to
positive supply voltage must be externally connected). When
the bus is free, both lines are HIGH. The output stages of
ISL6423 will have an open drain/open collector in order to
perform the wired-AND function. Data on the I
2
C bus can be
transferred up to 100kbps in the standard-mode or up to
400kbps in the fast-mode. The level of logic “0” and logic “1”
is dependent of associated value of V
DD
as per electrical
specification table. One clock pulse is generated for each
data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 4.
START and STOP Conditions
As shown in Figure 5, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
TABLE 1.
VSPEN VTOP VBOT SELVTOP VOUT (V)
0 x 0 0 13.3
0 x 1 0 14.3
0 0 x 1 18.3
0 1 x 1 19.3
100x13.3
101x14.3
110x18.3
111x19.3
SDA
SCL
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
FIGURE 4. DATA VALIDITY
SDA
SCL
START
CONDITION
FIGURE 5. START AND STOP WAVEFORMS
STOP
CONDITION
SP
ISL6423
