13
FN9191.2
December 5, 2008
Received Data (I
2
C bus READ MODE)
The ISL6423 can provide to the master a copy of the system
register information via the I
2
C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6423 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6423.
Not acknowledge, stopping the read mode
communication.
The read only bits of the register SR1 convey diagnostic
information about the ISL6423, as indicated in the Table 7.
Power–On I
2
C Interface Reset
The I
2
C interface built into the ISL6423 is automatically reset
at power-on. The I
2
C interface block will receive a power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I
2
C commands and the
system register SR1 thru SR4 are all initialized to zero, thus
keeping the power blocks disabled. Once the VCC rises
above UVLO, the POWER OK signal to the I
2
C is asserted
high, and the I
2
C interface becomes operative and the SR’s
can be configured by the main microprocessor. About
400mV of hysteresis is provided in the UVLO threshold to
avoid false triggering of the power-on reset circuit. (I
2
C
comes up with EN = 0; EN goes HIGH at the same time as
(or later than) all other I
2
C data for that PWM becomes
valid).
ADDR0 and ADDR1 Pins
Connecting these pin to GND the chip I
2
C interface address
is 0001000, but, it is possible to choose between four
different addresses by setting these pins to the logic levels
indicated in Table 11.
TABLE 10. CONTROL REGISTER SR4 CONFIGURATION
SR4H SR4M SR4L EN X X VTOP VBOT FUNCTION
0111XX00SR4 is selected
0 1 1 1 X X 0 0 VSPEN = SELVTOP = 0, Vout1 = 13V, Vboost1 = 13V + Vdrop
0 1 1 1 X X 0 1 VSPEN = SELVTOP = 0, Vout1 = 14V, Vboost1 = 14V + Vdrop
0 1 1 1 X X 1 0 VSPEN = SELVTOP = 0, Vout1 = 13V, Vboost1 = 13V + Vdrop
0 1 1 1 X X 1 1 VSPEN = SELVTOP = 0, Vout1 = 14V, Vboost1 = 14V + Vdrop
0 1 1 1 X X 0 0 VSPEN = 0, SELVTOP = 1, Vout1 = 18V, Vboost1 = 18V + Vdrop
0 1 1 1 X X 0 1 VSPEN = 0, SELVTOP = 1, Vout1 = 18V, Vboost1 = 18V + Vdrop
0 1 1 1 X X 1 0 VSPEN = 0, SELVTOP = 1, Vout1 = 19V, Vboost1 = 19V + Vdrop
0 1 1 1 X X 1 1 VSPEN = 0, SELVTOP = 1, Vout1 = 19V, Vboost1 = 19V + Vdrop
0 1 1 1 X X 0 0 VSPEN = 1, SELVTOP = X Vout1 = 13V, Vboost1 = 13V + Vdrop
0 1 1 1 X X 0 1 VSPEN = 1, SELVTOP = X Vout1 = 14V, Vboost1 = 14V + Vdrop
0 1 1 1 X X 1 0 VSPEN = 1, SELVTOP = X Vout1 = 18V, Vboost1 = 18V + Vdrop
0 1 1 1 X X 1 1 VSPEN = 1, SELVTOP = X Vout1 = 19V, Vboost1 = 19V + Vdrop
0 1 1 0 X X X X PWM and Linear for channel 1 disabled
NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.
TABLE 11. ADDRESS PIN CHARACTERISTICS
V
ADDR
ADDR1 ADDR0
V
ADDR
-1 “0001000” 0 0
V
ADDR
-2 “0001001” 0 1
V
ADDR
-3 “0001010” 1 0
V
ADDR
-4 “0001011” 1 1
ISL6423
14
FN9191.2
December 5, 2008
I
2
C Bit Description I
2
C Electrical Characteristics
BIT NAME DESCRIPTION
EN ENable Output for channels 1 and 2
VTOP Voltage TOP Select i.e., 18V/19V for channels 1 and 2
VBOT Voltage BOTtom Select i.e., 13V/14V for channels 1
and 2
ENT ENable Tone
MSEL Modulation SELect
DCL Dynamic Current Limit select
VSPEN Voltage Select Pin ENable
ISELH and
ISELL
Current limit “I” SELect High and Low bit
OTF Over Temperature Fault bit
CABF CABle Fault or open status bit.
OUVF Over and Under Voltage Fault status bit
OLF Over Load Fault status bit
BCF Backward Current Fault bit
TTH Tone THreshold is the OR of the signal pin TXT
TABLE 12.
PARAMETER
TEST
CONDITION MIN TYP MAX
Input Logic
High, VIH
SDA, SCL 2.0V
Input Logic
Low, VIL
SDA, SCL 0.8V
Input Logic
Current, IIL
SDA, SCL;
0.4V < V
DD
< 3.3V
10μA
Input Logic
Current IOL
VOL = 0.4V 3mA
Input
Hysteresis
SDA, SCL 165mV 200mV 235mV
SCL Clock
Frequency
0 100kHz 400kHz
Input Filter
Spike reject
50ns
ISL6423
15
FN9191.2
December 5, 2008
ISL6423
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
0 . 90 ± 0 . 1
5
C
0 . 2 REF
TYPICAL RECOMMENDED LAND PATTERN
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
( 24X 0 . 25 )
0 . 00 MIN.
( 20X 0 . 5 )
( 2 . 50 )
SIDE VIEW
( 3 . 8 TYP )
BASE PLANE
4
TOP VIEW
BOTTOM VIEW
712
24X 0 . 4 ± 0 . 1
13
4.00
PIN 1
18
INDEX AREA
24
19
4.00
2.5
0.50
20X
4X
SEE DETAIL "X"
- 0 . 05
+ 0 . 07
24X 0 . 23
2 . 50 ± 0 . 15
PIN #1 CORNER
(C 0 . 25)
1
SEATING PLANE
0.08 C
0.10
C
C
0.10 M C A B
A
B
(4X)
0.15
located within the zone indicated. The pin #1 indentifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:

ISL6423EVEZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers NOTCOMENDED FOR NEW DESIGN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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