6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
11
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
4832 drw 07
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
t
SC
t
HC
t
CKHZ
t
CKLZ
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
An An + 1 An + 2 An + 3
t
CYC2
t
CH2
t
CL2
R/
W
ADDRESS
CE
0
CLK
CE
1
UB, LB
(0-3)
(3)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
4832 drw 06
(1)
(1)
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
t
SB
t
HB
(4)
(1 Latency)
(5)
(5)
Timing Waveform of a Multi-Device Pipelined Read
(1,2)
Timing Waveform of Read Cycle for Pipelined Operation
(2)
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = V
IL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE
0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATA
OUT for Qn + 2 would be disabled (High-Impedance state).
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3389 for this waveform,
and are setup for depth expansion in this example. ADDRESS
(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = V
IL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.