DC252A Datasheet DC252A | P7-P9

DEMO MANUAL DC252

DESIGN-READY SWITCHER

OPERATIO

Low Current Modes and Synchronization

The FCB input pin, set by jumper JP1 and FCB/Sync

terminal E4, allows the selection of the low current oper-

ating mode and external frequency synchronization of the

switching regulator.

Tying the FCB pin to ground with JP1 forces the controller

into PWM or forced continuous mode. In forced continu-

ous mode, the output MOSFETs are always driven, regard-

less of output loading conditions. Operating in this mode

allows the switching regulator to source or sink current—

but be careful; when the output stage sinks current, power

is transferred back into the input supply terminals and the

input voltage rises.

Burst Mode operation is enabled when the voltage applied

to the FCB pin is greater than 0.8V (i.e., JP1 tied to INTV

)

or if the pin is left open. A comparator with a precision 0.8V

threshold allows the pin to be used to regulate a secondary

winding on the switching regulator’s output. A small

amount of hysteresis is included in the design of the

comparator to facilitate clean secondary operation. When

the resistively divided secondary output voltage falls be-

low the 0.8V threshold, the controller operates in the

forced continuous operating mode for as long as it takes

to bring the secondary voltage above the 0.8V + hysteresis

level.

The internal LTC1736 oscillator can be synchronized to an

external oscillator by clocking the FCB pin with a signal

above 1.5V

P-P

(Remember to remove jumper JP1). When

the LTC1736 is synchronized to an external frequency,

Burst Mode operation operation is disabled but cycle

skipping is allowed at low load currents, since current

reversal is inhibited. The bottom gate will come on every

10 clock cycles to ensure that the bootstrap capacitor C

is kept charged. The rising edge of an external clock

applied to the FCB pin starts a new cycle.

When the LTC1736 is synchronized to an external clock,

burst inhibit mode allows heavily discontinuous, low

audio noise, constant frequency operation down to ap-

proximately 1% of maximum designed load current. This

mode results in the elimination of switching frequency

subharmonics over 99% of the output load range. Switch-

ing cycles start to be dropped at approximately 1% of

maximum designed load current in order to maintain

proper output voltage.

The range of synchronization is from 240kHz to 350kHz

with C

OSC

= 47pF. Attempting to synchronize to a higher

frequency than 350kHz can result in inadequate slope

compensation and cause loop instability with high duty

cycles. If loop instability is observed while synchronized,

additional slope compensation can be obtained by simply

decreasing C

OSC

The following table summarizes the possible states avail-

able on the FCB/Sync pin:

FCB/SYNC PIN CONDITION

DC Voltage: 0V to 0.7V Burst Disabled/Forced Continuous

Current Reversal Enabled

DC Voltage: ≥ 0.9V Burst Mode Operation,

No Current Reversal

Feedback Resistors Regulating a Secondary Winding

Ext Clock: (0V to V

FCB/SYNC

) Burst Mode Operation Disabled

FCB/SYNC

> 1.5V) No Current Reversal

DC252 Modifications (MOSFETs)

The DC252 demo board has various modification provi-

sions. Additional pad locations are available for adding

extra output capacitors together with an extra footprint for

a parallel topside MOSFET.

When operating at high input voltages, the transition

losses of the topside MOSFET (M2) become very signifi-

cant. Be sure to consider power loss due to transition

losses as well as R

DS(ON)

losses. Don’t over specify the

topside MOSFET. (Refer to the LTC1736 data sheet for

details.)

Refer to the LTC1736 data sheet for further information on

the internal operation and functionality descriptions of the

IC.

DC252 Modifications (Output Capacitors)

Four Matsushita SP output capacitors are installed on the

demo board. Other output capacitors may freely be substi-

tuted provided they meet the load transient requirements.

OPTI-LOOP compensation allows the transient response

to be optiumized over a wide range of output capacitance

and ESR values while minimizing output capacitance.

DEMO MANUAL DC252

DESIGN-READY SWITCHER

The output capacitors are generally determined by ESR

(effective series resistance) and voltage rating rather than

capacitance. The ESR must be small enough that output

ripple voltage and any voltage droop due to high load

current transients stay within the specifications of the

CPU. The output capacitance must be large enough to hold

up the output voltage until the inductor current has ramped

up or down to its new value. With proper OPTI-LOOP

compensation components, the response time is opti-

mized and the output capacitance is minimized. The com-

pensation components installed on the demo board are

appropriate for the output capacitors specified in the parts

list.

Additional mounting locations exist for through hole Sanyo

OS-CON output capacitors, should they be desired. Com-

binations of different types of capacitors have proved to

yield cost effective solutions. ESL (equivalent series in-

ductance), typically not specified, can reduce the effec-

tiveness of the ESR at high load current slew rates, so be

careful in specifying the output capacitor.

Overcurrent Protection

The RUN/SS capacitor, C

SS1

is used initially to turn on and

limit the inrush current of the controller. After the control-

ler has been started and given adequate time to charge the

output capacitor and provide full load current, C

SS1

is used

as a short-circuit time-out circuit. If the output voltage falls

to less than 70% of its nominal value, C

SS1

begins dis-

charging on the assumption that the output is in an

overcurrent and/or short-circuit condition. If the condition

lasts for a long enough period, as determined by the size

of C

SS1

, the controller will be shut down until the RUN/SS

pin voltage is recycled. This built-in latchoff can be over-

ridden by providing >5µA pull-up at a compliance of 4V to

the RUN/SS pin by installing jumper JP2. This current

shortens the soft-start period but also prevents net dis-

charge of the RUN/SS capacitor during an overcurrent

and/or short-circuit condition.

Foldback current limiting is activated when the output

voltage falls below 70% of its nominal level, whether or not

the short-circuit latchoff circuit is enabled.

With the overcurrent latchoff enabled, a slow ramp on the

input voltage may cause the circuit to latch off. Simply re-

cycle the run pin to start. Refer to the LTC1736 data sheet

for details.

Overvoltage Protection

The output is protected from overvoltage by a “soft-latch.”

When the output voltage exceeds the regulation value by

more than 7.5%, the synchronous MOSFET turns on, and

remains on for as long as the overvoltage condition is

present. If the output voltage returns to a safe level, normal

operation resumes. This self-resetting action prevents

"nuisance trips" due to momentary transients and elimi-

nates the need for the Schottky diode that is necessary

with conventional OVP to prevent V

OUT

reversal.

Because of the inherent self-resetting action of the soft-

latch, dynamic changing of the VID control bits does not

latch off the LTC1736. When a new output voltage is set via

the VID bits, the control loop simply adjusts the output

voltage and the overvoltage protection threshold to this

new level without causing a fault.

The overvoltage threshold tracks the new output voltage,

protecting the load at all times. Figure 3a and Figure 3b

both show an example of a dynamic VID code change

resulting in a programmed output voltage change from

1.5V to 1.3V at a constant 5 ampere load current. At the

instant the VID code is changed, the control loop begins to

respond to the new output voltage, and the power-good

output is asserted low since the new programmed output

voltage is outside the 7.5% window. When the new output

voltage is within 7.5% of its new programmed value, the

power-good signal goes high. Figure 3a shows a VID code

change with the FCB pin low (Burst Mode operation

disabled). Figure 3b shows a dynamic VID code change

with Burst Mode operation active. If dynamic VID changes

are required and Burst Mode operation is desired, connect

the PGOOD output (E1) to the FCB/Sync input (E4) and

remove jumper JP1. This connection automatically forces

continuous operation whenever the power-good output is

low, providing fast response to VID changes regardless of

load current.

Active Loads— Beware

Beware of active loads! They are convenient but problem-

atic. Some active loads do not turn on until the applied

OPERATIO

DEMO MANUAL DC252

DESIGN-READY SWITCHER

voltage rises above 0.1V to 0.8V. The turn-on may be

delayed as well. A switching regulator with soft-start may

appear to start up, then shut down and, eventually, reach

the correct output voltage. What happens is as follows: at

switching regulator turn-on, the output voltage is below

the active load’s turn-on requirements. The switching

regulator’s output rises to the correct output voltage level

due to the inherent delay in the active load. The active load

turns on after its internal delay and then pulls down the

switching regulator’s output because the switcher is in its

soft-start interval. The switching regulator’s output may

come up at some later time when the soft-start interval has

passed.

A switching regulator with foldback current limit will also

have difficulty with the unrealistic I-V characteristic of the

active load. Foldback current limiting will reduce the

output current available as the output voltage drops below

a threshold level (this level is 70% of nominal V

OUT

for the

LTC1736). This reduction in available output current will

result in the active load immediately pulling down the

output because the active load’s current demand remains

constant as the output voltage decreases. Most actual

loads do not behave like the active load I-V characteristics.

Actual loads normally have a V

• C • f dependency, where

C is internal chip capacitance and f is the frequency of

operation. To alleviate the active-load problem during

testing, the active load should be initially programmed to

a much lower current value until the switching regulator’s

soft-start interval has passed and then increased to the

higher level. The switching regulator will supply the in-

creased current required according to the transient re-

sponse of the switching regulator. Output capacitance

needs to be sufficient to accommodate the current step

during the transient period, keeping the output voltage at

or above the foldback threshold of 70%.

Checking Transient Response

OPTI-LOOP compensation effectively removes the con-

straints placed on C

OUT

by other controllers (such as

restrictions on very low ESRs). The output capacitors

used in this demo board have very low ESRs; other types

may be substituted but be carefull to measure the load step

transient response and verify the specfications on output

voltage continue to be met during transients.

A partial list of low ESR capacitors that are suitable for this

application is included in the parts list. Each has its own

cost, size, ESL and other performance trade offs. Combi-

nations of capacitors have been shown to work well, too,

so feel free to experiment. An example of a combination

that works well is an OS-CON, 820µF/4V capacitor in

parallel with a 180µF/4V Matsushita SP series capacitor.

The SP capacitor tames the ESL-induced characteristic of

OPERATIO

Figure 3a. Dynamic VID Change, Burst Mode Operation Defeated Figure 3b. Dynamic VID Change, Burst Mode Operation Enabled

252 F03a

PGOOD

5V/DIV

OUT

100mV/

DIV

5A/DIV

252 F03b

PGOOD

5V/DIV

OUT

100mV/

DIV

5A/DIV

P1-P3 P4-P6 P7-P9 P10-P12

DC252A

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Power Management IC Development Tools LTC1736CG - 5 Bit, VID CPU Power Convert

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DC252A