Power-OK Signal
(POK, MAX8598/MAX8599 Only)
The power-OK signal (POK) is an open-drain output that
goes high impedance when FB is above 91% of its nom-
inal threshold. There is an eight clock-cycle delay before
POK goes high impedance. For 500kHz switching fre-
quency, this delay is typically 16µs. To obtain a logic
voltage output, connect a pullup resistor from POK to
AVL. A 100kΩ resistor works well for most applications.
If unused, connect POK to GND or leave it unconnected.
Enable and Soft-Start
The MAX8597/MAX8598/MAX8599 are enabled using
the EN input. A logic high on EN enables the output of
the IC. Conversely, a logic low on EN disables the out-
put. On the rising edge of EN, the controllers enter soft-
start. Soft-start gradually ramps up the reference
voltage seen at the error amplifier to control the output
rate of rise and reduce the inrush current during start-
up. The soft-start period is determined by a capacitor
connected from SS to GND (C6 in Figure 1). A 5µA cur-
rent source charges the external capacitor to the refer-
ence voltage (0.6V or V
REFIN
). The capacitor value is
determined as follows:
where t
SS
is the soft-start time in seconds and V
FB
is
0.6V or V
REFIN
. The output reaches regulation when
soft-start is completed.
Output Undervoltage Protection (UVP)
Output UVP begins when the controller is at its current
limit and V
FB
is 30% below its nominal threshold. This
condition causes the controller to drive DH and DL low
and discharges the soft-start capacitor with a 5µA pull-
down current until V
SS
reaches 50mV. Then the con-
troller begins in soft-start mode. If the overload
condition still exists, the UVP process begins again. The
result is “hiccup” mode, where the controller attempts to
restart periodically as long as the overload condition
exists. In hiccup mode, the soft-start capacitor voltage
ramps up to 112% of the nominal V
FB
threshold and
then ramps down to 50mV. For the MAX8597, V
REFIN
must be greater than 450mV to trigger UVP. The soft-
start capacitor voltage then ramps up to 112% of V
REFIN
and then down to 50mV.
Output Overvoltage Protection
(OVP, MAX8599)
The output voltage is continuously monitored for over-
voltage (MAX8599 only). If the output voltage is more
than 117% of its nominal set value, OVP is triggered
after a 12µs (typ) delay. The MAX8599 latches DH low
to turn off the high-side MOSFET, and DL high to turn
on the low-side MOSFET to clamp the output to PGND.
The latch is reset either by toggling EN or by cycling V+
below the UVLO threshold. Note that DL latching high
causes a negative spike at the output due to the energy
stored in the output LC at the instant of OVP trip. If the
load cannot tolerate this negative spike, add a power
Schottky diode across the output to act as a reverse
polarity clamp.
Thermal-Overload Protection
Thermal-overload protection limits the total power dissi-
pation in the MAX8597/MAX8598/MAX8599. When the
junction temperature exceeds +160°C, a thermal sen-
sor shuts down the device, forcing DH and DL low,
allowing the IC to cool. The thermal sensor turns the
part on after the junction temperature cools by 10°C,
resulting in a pulsed output during continuous thermal-
overload conditions. During a thermal event, the switch-
ing converter is turned off, the reference is turned off,
the VL regulator is turned off, POK is high impedance,
and the soft-start capacitor is discharged.
