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RAA207701GBM#HC0

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
RAA207700GBM/7701GBM/7702GBM
R07DS0891EJ0100 Rev.1.00 Page 19 of 25
Aug 02, 2013
Design Example
(VIN = 12 V, VCIN = 5 V, Vout = 1.2 V, Fsw = 500 kHz (at CCM), L = 0.47 mH)
U6
RAA207700GBM
VCIN
A1
SGND
A2
FB
A3
LS_IN
A4
LS_OUT
A5
VIN_C2
C2
VIN_C3
C3
VIN_C4
C4
VIN_C5
C5
VIN_D5
D5
SS
B4
ON/OFF
B5
BOOT
B1
SET
B2
PGOOD
B3
SW_D1
D1
SW_D2
D2
SW_D3
D3
SW_D4
D4
SW_C1
C1
SW_E1
E1
SW_F1
F1
SW_F2
F2
SW_F3
F3
SW_G1
G1
PGND_E2
E2
PGND_E3
E3
PGND_E4
E4
PGND_E5
E5
PGND_F4
F4
PGND_F5
F5
PGND_G2
G2
PGND_G3
G3
PGND_G4
G4
PGND_G5
G5
+12V
LS_OUT
LS_IN
ON/OFF
Vout
R3
51k
C1
1m/10V
+5V
0.1
m/25V
C2
C101 10m
/16V
C111 22
m/6.3V
C112
22m/6.3V
C113 22m
/6.3V
C114 22m
/6.3V
C115
22m
/6.3V
C102 10m/16V
C103 10m/16V
0.01
m
/25V
C4
0.47mH
1000p/25V
C5
3300p/10V
C3
R4 30k
R6 15k
R5
3.9
R1
13k
L1
R2
27k
1. Setting of ton (constant on time)
In this condition, calculated on time is from equation (1),
Calculated ton: 1.2 V / 12 V • (1 / 500 kHz) = 200 ns
From equation (3),
Calculated R4 = (1.2V / (12 V • 500 kHz) – 60 ns) • (12 V – 2 V) / (50 pF • 1 V) = 28 kW
so choose R4 = 30 kW from E24 series.
So, actual on pulse ton is decided by equation (2),
Constant on time: ((50 pF • 1 V / (12 V – 2 V)) • 30 kW + 60 ns = 210 ns
2. Setting of ripple injection resistance
Voltage ripple on FB pin needs to be more than 15 mV. Here, C4 = 0.01 mF, C5 = 1000 pF and ESR of output cap =
0.5 mW. To obtain 15 mV additional ripple on FB pin from R6, C4 and C5 network circuit, R6 is calculated by
equation (10).
Calculated R6: (12 V – 1.2 V) • 210 ns / (15 mV • 0.01 mF) = 15.1 kW
So choose R6 = 15 kW from E24 series and actual ripple voltage from injection circuit becomes 15.1 mV.
So, Total ripple voltage on FB pin is calculate by equation (13),
Total ripple voltage:
(12 V – 1.2 V) • 210 ns / (15 kW • 0.01 mF) + (12 V – 1.2 V) • 210 ns / 0.47 mH • 0.5 mW =17.5 mV
3. Setting of output voltage resistor
From above setting, effective FB voltage is from equation (15),
Effective FB voltage: 800 mV + 17.5 mV / 2 = 808.8 mV
When R1 = 13 kW, R2 is decided from equation (15).
R2 = 13 kW / ((1.2 V / 808.8 mV) – 1) = 26.8 kW
So, choose R2 = 27 kW from E24 series.
RAA207700GBM/7701GBM/7702GBM
R07DS0891EJ0100 Rev.1.00 Page 20 of 25
Aug 02, 2013
4. Stability criteria confirmation
For output capacitor, please confirm stability criteria. Stability criteria from equation (11),
1 / (2p • 0.01 mF • 500 kHz) = 32 W << 1 / (2p • 1000 pF • 500 kHz) = 318 W << 13 kW • 27 kW / (13 kW
+ 27 kW) = 8.8 kW
so, above criteria is satisfied.
For output capacitor, please confirm stability criteria. Stability criteria from equation (12),
Cout > (210 ns / 2) • 15 kW • 0.01 mF / 0.47 mH = 34 mF
So, choose 110 mF (22 mF ´ 5 pcs.) for output capacitor. Here, please consider voltage dependence of capacitor.
If you cannot satisfy above criteria, please consider below changes.
¾ increase L or Cout value
¾ increase frequency (decrease constant on time)
¾ change Rf value.
5. Other components
C1 = 1 mF / 10 V and C2 = 0.1 mF / 25 V are recommended. C3 decides soft start period from equation (5). R5 is
decided from the table in “Boot Resistance” section. Input and output capacitors are decided considering voltage
ripple, current ripple and voltage tolerance.
RAA207700GBM/7701GBM/7702GBM
R07DS0891EJ0100 Rev.1.00 Page 21 of 25
Aug 02, 2013
Board Layout Example (RAA207700GBM)
Board layer example: 4 layer, internal 2nd and 3rd layer are used for GND plane.
SW
plane
SW
plane
GND plane
GND plane
VIN plane
Top Layer Bottom Layer
VIN plane
Vout
plane
1. Power part
¾ Input capacitor should be placed close to VIN and PGND pin to reduce switching noise and to improve the
efficiency.
¾ Many thermal via should be placed on VIN, SW and PGND planes to spread heat to board. Furthermore, VIN,
SW planes on bottom layer are effective for thermal spread (If available).
2. Control part
¾ Decoupling capacitor between VCIN and SGND should be placed as close as possible to the chip in order to
stable operation.
¾ Also, SGND, PGND via should be placed as close as possible to the chip, and connect each pin low impedance
by internal GND plane.
¾ FB resistance should be placed close to chip and FB wiring should be short to avoid noise. Furthermore,
additional ripple circuit wiring should be kept away from high dv/dt plane such as SW and BOOT wiring.
¾ To ensure the reliability of chip - board connection, we recommend Solder Mask Defined (SMD) layout. But
you can also use Non-Solder Mask Defined (NSMD) layout as far as you can ensure the reliability. In the case of
SMD layout, we recommend below size.
Solder resist open size: 280 mm, Land size: 280 mm + 50 to 100 mm (please consider processing accuracy)
3. Line SW
¾ When Line SW function is not used, no need to wiring LS_IN, LS_OUT pin.
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RAA207701GBM#HC0

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Buy RAA207701GBM#HC0
Manufacturer:
Renesas Electronics
Description:
Switching Voltage Regulators Power - Mini POL
Lifecycle:
New from this manufacturer.
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