Si4704/05-C40
4 Rev. 1.0
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage V
DD
2.7 5.5 V
Interface Supply Voltage V
IO
1.85 3.6 V
Digital Power Supply Powerup
Rise Time
V
DRISE
10 µs
Interface Power Supply Powerup
Rise Time
V
IORISE
10 µs
Ambient Temperature T
A
–20 25 85 C
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V
DD
= 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings
1,2
Parameter Symbol Value Unit
Supply Voltage
V
DD
–0.5 to 5.8 V
Interface Supply Voltage V
IO
–0.5 to 3.9 V
Input Current
3
I
IN
10 mA
Input Voltage
3
V
IN
–0.3 to (V
IO
+ 0.3) V
Operating Temperature T
OP
–40 to 95 C
Storage Temperature T
STG
–55 to 150 C
RF Input Level
4
0.4 V
PK
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended
operating conditions for extended periods may affect device reliability.
2. The Si4704/05 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should be done only at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pin, FMI.
Si4704/05-C40
Rev. 1.0 5
Table 3. DC Characteristics
(V
DD
= 2.7 to 5.5 V, V
IO
= 1.85 to 3.6 V, T
A
= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
FM Receiver to Line Output
Supply Current
1
I
FM
—19.222mA
Supply Current
2
I
FM
Low SNR level 19.9 23 mA
RDS Supply Current
1
I
FM
—19.223mA
Supplies and Interface
Interface Supply Current I
IO
—320600µA
V
DD
Powerdown Current I
DDPD
—1020 µA
V
IO
Powerdown Current I
IOPD
SCLK, RCLK inactive 1 10 µA
High Level Input Voltage
3
V
IH
0.7 x V
IO
—V
IO
+0.3 V
Low Level Input Voltage
3
V
IL
–0.3 0.3 x V
IO
V
High Level Input Current
3
I
IH
V
IN
=V
IO
=3.6V 10 10 µA
Low Level Input Current
3
I
IL
V
IN
=0V,
V
IO
=3.6V
–10 10 µA
High Level Output Voltage
4
V
OH
I
OUT
=50A 0.8xV
IO
——V
Low Level Output Voltage
4
V
OL
I
OUT
= –500 µA 0.2 x V
IO
V
Notes:
1. Guaranteed by characterization.
2. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Si4704/05-C40
6 Rev. 1.0
Figure 1. Reset Timing Parameters for Busmode Select
Table 4. Reset Timing Characteristics
1,2,3
(V
DD
= 2.7 to 5.5 V, V
IO
= 1.85 to 3.6 V, T
A
= –20 to 85 °C)
Parameter Symbol Min Typ Max Unit
RST
Pulse Width and GPO1, GPO2/INT Setup to RST
t
SRST
100 µs
GPO1, GPO2/INT
Hold from RST t
HRST
30 ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST
, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST
.
4. If GPO1 and GPO2 are actively driven by the user, then minimum t
SRST
is only 30 ns. If GPO1 or GPO2 is high
impedance, then minimum t
SRST
is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull
GPO1 high and GPO2 low.
70%
30%
GPO1
70%
30%
GPO2/
INT
70%
30%
t
SRST
RST
t
HRST

SI4705-C40-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Tuners Si4705 rev C FM Radio Tuner w/ RDS/RBDS, dig out, internal antenna 3x3x0.55 20-pin QFN, lead free
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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