VIPER50A Datasheet VIPER50SP, VIPER50A, VIPER50A(022Y) | P13-P15

Obsolete Product(s) - Obsolete Product(s)

13/23

VIPer50/SP - VIPer50A/ASP

UVLO logic, the device turns into active mode and

starts switching.

The start up current generator is switched off, and

the converter should normally provide the needed

current on the V

pin through the auxiliary

winding of the transformer, as shown on figure 15.

In case of abnormal condition where the auxiliary

winding is unable to provide the low voltage supply

current to the V

pin (i.e. short circuit on the

output of the converter), the external capacitor

discharges itself down to the low threshold voltage

DDoff

of the UVLO logic, and the device gets back

to the inactive state where the internal circuits are

in standby mode and the start up current source is

activated. The converter enters an endless start

up cycle, with a start-up duty cycle defined by the

ratio of charging current towards discharging when

the VIPer50/50A tries to start. This ratio is fixed by

design from 2 to 15, which gives a 12% start up

duty cycle while the power dissipation at start up is

approximately 0.6 W, for a 230 Vrms input voltage.

This low value of start-up duty cycle prevents the

stress of the output rectifiers and of the

transformer when in short circuit.

The external capacitor C

VDD

on the V

pin must

be sized according to the time needed by the

converter to start up, when the device starts

switching. This time t

depends on many

parameters, among which transformer design,

output capacitors, soft start feature and

compensation network implemented on the COMP

pin. The following formula can be used for defining

the minimum capacitor needed:

where:

is the consumption current on the V

when switching. Refer to specified I

DD1

and I

DD2

values.

is the start up time of the converter when the

device begins to switch. Worst case is generally at

full load.

DDhyst

is the voltage hysteresis of the UVLO

logic. Refer to the minimum specified value.

Soft start feature can be implemented on the

COMP pin through a simple capacitor which will

also be used as the compensation network. In this

case, the regulation loop bandwidth is rather low,

because of the large value of this capacitor. In

case of a large regulation loop bandwidth is

mandatory, the schematics in figure 16 can be

used. It mixes a high performance compensation

network together with a separate high value soft

start capacitor. Both soft start time and regulation

loop bandwidth can be adjusted separately.

If the device is intentionally shut down by putting

the COMP pin to ground, the device is also

performing start-up cycles, and the V

voltage is

oscillating between V

DDon

and V

DDoff

This voltage can be used for supplying external

functions, provided that their consumption doesn’t

exceed 0.5mA. Figure 17 shows a typical

application of this function, with a latched shut

down. Once the "Shutdown" signal has been

activated, the device remains in the off state until

the input voltage is removed.

VDD

DDhyst

--------------------------

Figure 15: Behavior of the high voltage current source at start-up

Ref.

UNDERVOLTAGE

LOCK OUT LOGIC

15 mA1 mA

3 mA

2 mA

15 mA

VDD

DRAIN

SOURCE

VIPer50

Auxiliary primary

winding

VDD

VDDoff

VDDon

Start up duty cycle ~ 12%

CVDD

FC00320

Obsolete Product(s) - Obsolete Product(s)

14/23

VIPer50/SP - VIPer50A/ASP

TRANSCONDUCTANCE ERROR AMPLIFIER

The VIPer50/50A includes a transconductance

error amplifier. Transconductance Gm is the

change in output current (I

COMP

) versus change in

input voltage (V

). Thus:

The output impedance Z

COMP

at the output of this

amplifier (COMP pin) can be defined as:

This last equation shows that the open loop gain

VOL

can be related to G

and Z

COMP

VOL

= G

x Z

COMP

where G

value for VIPer50/50A is 1.5 mA/V

typically.

is well defined by specification, but Z

COMP

and

therefore A

VOL

are subject to large tolerances. An

impedance Z can be connected between the

COMP pin and ground in order to define more

accurately the transfer function F of the error

amplifier, according to the following equation, very

similar to the one above:

(S)

= Gm x Z(S)

The error amplifier frequency response is reported

in figure 10 for different values of a simple

resistance connected on the COMP pin. The

unloaded transconductance error amplifier shows

an internal Z

COMP

of about 330 K

Ω

. More complex

impedance can be connected on the COMP pin to

achieve different compensation laws. A capacitor

will provide an integrator function, thus eliminating

the DC static error, and a resistance in series

leads to a flat gain at higher frequency, insuring a

correct phase margin. This configuration is

illustrated in figure 18.

As shown in figure 18 an additional noise filtering

capacitor of 2.2 nF is generally needed to avoid

any high frequency interference.

It can also be interesting to implement a slope

compensation when working in continuous mode

with duty cycle higher than 50%. Figure 19 shows

such a configuration. Note that R1 and C2 build

the classical compensation network, and Q1 is

injecting the slope compensation with the correct

polarity from the oscillator sawtooth.

EXTERNAL CLOCK SYNCHRONIZATION

The OSC pin provides a synchronisation

capability, when connected to an external

frequency source. Figure 20 shows one possible

schematic to be adapted depending on the

specific needs. If the proposed schematic is used,

the pulse duration must be kept at a low value

(500ns is sufficient) for minimizing consumption.

The optocoupler must be able to provide 20mA

through the optotransistor.

PRIMARY PEAK CURRENT LIMITATION

The primary I

DPEAK

current and, as resulting

effect, the output power can be limited using the

simple circuit shown in figure 21. The circuit based

on Q1, R

and R

clamps the voltage on the

∂I

COMP

∂V

------------------------

COMP

∂V

COMP

∂I

COMP

---------------------------

---------

∂ V

COMP

∂V

---------------------------

Figure 16: Mixed Soft Start and Compensation Figure 17: Latched Shut Down

13V

OSC

COMP SOURCE

DRAI NVDD

VIPer50

AUXILIARY

WINDING

FC00331

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

Shutdown

R2R3

FC00340

Obsolete Product(s) - Obsolete Product(s)

15/23

VIPer50/SP - VIPer50A/ASP

COMP pin in order to limit the primary peak current

of the device to a value:

where:

The suggested value for R

is in the range of

220K

Ω

OVER-TEMPERATURE PROTECTION:

Over-temperature protection is based on chip

temperature sensing. The minimum junction

temperature at which over-temperature cut-out

occurs is 140

C while the typical value is 170

The device is automatically restarted when the

junction temperature decreases to the restart

temperature threshold that is typically 40

C below

the shutdown value (see figure 8).

DPEAK

COMP

0.5

–

-------------------------------------

COMP

0.6

----------------------

Figure 18: Typical Compensation Network

Figure 20: External Clock Synchronization

Figure 19: Slope Compensation

Figure 21: Current Limitation Circuit Example

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

FC00351

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

R1R2

C1 R3

FC00361

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

10 k

Ω

FC00370

13V

OSC

COMP SOURCE

DRAINVDD

VIPer50

FC00380

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

VIPER50A

Mfr. #:

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AC/DC Converters 700V 1.5A SMPS

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