16
LTC3778
3778f
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a short-
circuit by the current foldback circuitry and latchoff
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5µA to the RUN/SS pin. The additional
current prevents the discharge of C
SS
during a fault and
also shortens the soft-start period. Using a resistor to V
IN
as shown in Figure 6a is simple, but slightly increases
shutdown current. Connecting a resistor to INTV
CC
as
shown in Figure 6b eliminates the additional shutdown
current, but requires a diode to isolate C
SS
. Any pull-up
network must be able to maintain RUN/SS above the 4V
maximum latch-off threshold and overcome the 4µA
maximum discharge current.
with the resistances of L and the board traces to obtain the
DC I
2
R loss. For example, if R
DS(ON)
= 0.01 and
R
L
= 0.005, the loss will range from 15mW to 1.5W
as the output current varies from 1A to 10A for a 1.5V
output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss (1.7A
–1
) V
IN
2
I
OUT
C
RSS
f
3. INTV
CC
current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply-
ing INTV
CC
current through the EXTV
CC
pin from a high
efficiency source, such as an output derived boost net-
work or alternate supply if available.
4. C
IN
loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I
2
R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C
OUT
ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to I
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
APPLICATIO S I FOR ATIO
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Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
3.3V OR 5V RUN/SS
V
IN
INTV
CC
RUN/SS
D1
(6a) (6b)
D2*
C
SS
R
SS
*
C
SS
*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF
R
SS
*
3778 F06
2N7002
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3778 circuits:
1. DC I
2
R losses. These arise from the resistances of the
sense resistor, MOSFETs, inductor and PC board traces
and cause the efficiency to drop at high output currents. In
continuous mode the average output current flows through
L, but is chopped between the top and bottom MOSFETs.
If the two MOSFETs have approximately the same R
DS(ON)
,
then the resistance of one MOSFET can simply be summed
17
LTC3778
3778f
APPLICATIO S I FOR ATIO
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During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components shown in Figure 7
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Linear Technology Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V
IN
= 7V to 28V (15V nominal), V
OUT
= 2.5V
±5%, I
OUT(MAX)
= 10A, f = 250kHz. First, calculate the
timing resistor with V
ON
= V
OUT
:
R
kHz pF
k
ON
=
()()
=
1
250 10
400
and choose the inductor for about 40% ripple current at
the maximum V
IN
:
L
V
kHz A
V
V
H=
()()()
25
250 0 4 10
1
25
28
23
.
.
.
.
Selecting a standard value of 1.8µH results in a maximum
ripple current of:
∆=
()
µ
()
=I
V
kHz H
V
V
A
L
25
250 1 8
1
25
28
51
.
.
.
.
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R
DS(ON)
= 0.0083 (NOM) 0.010 (MAX),
θ
JA
= 40°C/W) yields a nominal sense voltage of:
V
SNS(NOM)
= (10A)(1.3)(0.0083) = 108mV
Tying V
RNG
to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ
150°C
= 1.5:
I
mV
AA
LIMIT
()
()
+
()
=
146
15 0010
1
2
51 12
..
.
and double check the assumed T
J
in the MOSFET:
P
VV
V
AW
BOT
=
()()
()
=
28 2 5
28
12 15 0010 197
2
–.
.. .
T
J
= 70°C + (1.97W)(40°C/W) = 149°C
Because the top MOSFET is on for such a short time, an
Si4884 R
DS(ON)(MAX)
= 0.0165, C
RSS
= 100pF will be
sufficient. Checking its power dissipation at current limit
with ρ
100°C
= 1.4:
P
V
V
A
VApFkHz
WWW
TOP
=
()()
()
+
()( )( )( )( )
=+=
25
28
12 1 4 0 0165
1 7 28 12 100 250
030 040 07
2
2
.
..
.
...
T
J
= 70°C + (0.7W)(40°C/W) = 98°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C
IN
is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013 to minimize output voltage changes due to induc-
tor ripple current and load steps. The ripple voltage will be
only:
V
OUT(RIPPLE)
= I
L(MAX)
(ESR)
= (5.1A) (0.013) = 66mV
However, a 0A to 10A load step will cause an output
change of up to:
V
OUT(STEP)
= I
LOAD
(ESR) = (10A) (0.013) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.
18
LTC3778
3778f
Active Voltage Positioning
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage at or above the regulation point at zero load, and
below the regulation point at full load, one can use more
of the error budget for the load step. This allows one to
reduce the number of output capacitors by relaxing the
ESR requirement.
For example, in a 20A application, six 0.015 capacitors
are required in parallel to keep the output voltage within a
100mV tolerance:
±
()
=20
1
6
0 015 50 100AmVmV.
Using active voltage positioning, the same specification
can be met with only three capacitors. In this case, the load
step will cause an output voltage change of:
∆=
()
()
=VA mV
OUT STEP()
.20
1
3
0 015 100
APPLICATIO S I FOR ATIO
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20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
RUN/SS
V
ON
PGOOD
V
RNG
I
TH
FCB
SGND
I
ON
V
FB
EXTV
CC
BOOST
TG
SW
SENSE
+
SENSE
PGND
BG
DRV
CC
INTV
CC
V
IN
LTC3778
+
M2
Si4874
M1
Si4884
L1, 1.8µH
D1
B340A
C
OUT1-2
180µF
4V
×2
C
OUT3
22µF
6.3V
X7R
C
IN
10µF
35V
×3
V
IN
5V TO 28V
V
OUT
2.5V
10A
C
SS
0.1µF
C
C1
500pF
C
ON
,
0.01µF
C
C2
100pF
C
VCC
4.7µF
C
F
0.1µF
C
B
0.22µF
R
C
20k
R1
12.7k
R
ON
400k
R2
40.2k
R
F
1
D
B
CMDSH-3
3778 F07
C
IN
: UNITED CHEMICON THCR60EIHI06ZT
C
OUT1-2
: CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-1R8MC-H
R
PG
100k
R3
11k
R4
39k
+
Figure 7. Design Example: 2.5V/10A at 250kHz
By positioning the output voltage at the regulation point at
no load, it will drop 100mV below the regulation point after
the load step. However, when the load disappears or the
output is stepped from 20A to 0A, the 100mV is recovered.
This way, a total of 100mV change is observed on V
OUT
in
all conditions, whereas a total of ±100mV or 200mV is
seen on V
OUT
without voltage positioning while using only
three output capacitors.
Implementing active voltage positioning requires setting a
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resis-
tance, it is prudent to use a sense resistor with active
voltage positioning. In order to minimize power lost in this
resistor, a low value of 0.002 is chosen. The nominal
sense voltage will now be:
V
SNS(NOM)
= (0.002)(20A) = 40mV
To maintain a reasonable current limit, the voltage on the
V
RNG
pin is reduced to 0.5V by connecting it to a resistor
divider from INTV
CC
, corresponding to a 50mV nominal
sense voltage.
Next, the gain of the LTC3778 error amplifier must be
determined. The change in I
TH
voltage for a corresponding
change in the output current is:

LTC3778EF#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Wide Operating Rng, No RSENSE Buck Cntr
Lifecycle:
New from this manufacturer.
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