MC100LVEL12DR2G

© Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 4
1 Publication Order Number:
MC100LVEL12/D
MC100LVEL12
3.3V ECL Low Impedance
Driver
Description
The MC100LVEL12 is a low impedance drive buffer. With two
pairs of OR/NOR outputs the device is ideally suited for high drive
applications such as memory addressing. The device is functionally
equivalent to the EL12 device and operates from a 3.3 V power supply.
With propagation delays equivalent to the EL12, the LVEL12 is
ideally suited for those applications which require the ultimate in
AC performance in a low voltage environment.
Features
445 ps Propagation Delay
Dual Outputs for 25 Drive Applications
ESD Protection: >4 kV Human Body Model,
> 200 V Machine Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 3.0 V to 3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with All Inputs Open or at V
EE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 83 devices
PbFree Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
KV12
ALYWG
G
SOIC8
D SUFFIX
CASE 751
1
8
TSSOP8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
KVL12
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
4A M G
G
14
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M
= Date Code
G = PbFree Package
MC100LVEL12
http://onsemi.com
2
Figure 1. Logic Diagram and Pinout Assignment
1
2
3
45
6
7
8
D
0
V
EE
V
CC
Q
a
Q
b
D
1
Q
a
Q
b
D0, D1 ECL Data Inputs
Qa, Qa
; Qb, Qb ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
Table 1. PIN DESCRIPTION
PIN FUNCTION
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND)
or leave unconnected, floating open.
Table 2. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V 8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
6 to 0
6 to 0
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (JunctiontoCase) Standard Board 8 SOIC 41 to 44 ± 5% °C/W
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (JunctiontoCase) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder Pb
PbFree
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
JC
Thermal Resistance (JunctiontoCase) (Note 1) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
MC100LVEL12
http://onsemi.com
3
Table 3. LVPECL DC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0.0 V (Note 2)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 17 24 17 24 18 25 mA
V
OH
Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage 1490 1825 1490 1825 1490 1825 mV
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
3. Outputs are terminated through a 50 resistor to V
CC
2.0 V.
Table 4. LVNECL DC CHARACTERISTICS V
CC
= 0.0 V; V
EE
= 3.3 V (Note 4)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 17 24 17 24 18 25 mA
V
OH
Output HIGH Voltage (Note 5) 1085 1005 880 1025 955 880 1025 955 880 mV
V
OL
Output LOW Voltage (Note 5) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mV
V
IH
Input HIGH Voltage 1165 880 1165 880 1165 880 mV
V
IL
Input LOW Voltage 1810 1475 1810 1475 1810 1475 mV
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
5. Outputs are terminated through a 50 resistor to V
CC
2.0 V.
Table 5. AC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
= 3.3 V (Note 6)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
Maximum Toggle Frequency TBD TBD TBD GHz
t
PLH
t
PHL
Propagation Delay to
Output
310 580 310 445 580 320 590 ps
t
JITTER
CycletoCycle Jitter TBD TBD TBD ps
t
r
t
f
Output Rise/Fall Times Q
(20% 80%)
230 400 550 230 400 550 230 400 550 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. V
EE
can vary ±0.3 V.

MC100LVEL12DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates 3.3V ECL Low Impedance Driver
Lifecycle:
New from this manufacturer.
Delivery:
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